From 8cac4b62d9bae742e14f40381e066838d2119d43 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Thu, 28 May 2015 05:40:41 +0000
Subject: [PATCH] - fixed port map (Xilinx bug)

git-svn-id: http://moon:8086/svn/vhdl/trunk@1252 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/uart/uart_xil.vhd | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/lib/uart/uart_xil.vhd b/lib/uart/uart_xil.vhd
index 989bd55..e1cefc0 100644
--- a/lib/uart/uart_xil.vhd
+++ b/lib/uart/uart_xil.vhd
@@ -35,8 +35,11 @@ signal tx_complete		: std_logic;
 signal tx_empty			: std_logic;
 signal tx_full			: std_logic;
 signal tx_half_full		: std_logic;
-
+
+signal data_out			: std_logic_vector(7 downto 0);
 begin
+
+dout 	<= unsigned(data_out);
 
 baud_timer:
 process(clk)
@@ -73,7 +76,7 @@ inst_uart_rx: entity work.uart_rx
 	port map
 	(
 		serial_in			=> ser_rx,
-		unsigned(data_out)	=> dout,
+		data_out				=> data_out,
 		read_buffer			=> re,
 		reset_buffer		=> rst,
 		en_16_x_baud		=> en_16_x_baud,