- cleaned up interfaces

- prepared for separating phy

git-svn-id: http://moon:8086/svn/vhdl/trunk@1188 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
2015-05-24 07:28:22 +00:00
parent 4896105caf
commit 88d51424b9
6 changed files with 75 additions and 99 deletions
+15 -22
View File
@@ -39,17 +39,12 @@ entity sdram_cmd is
rst : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
u_tag_in : in user_tag_t;
u_tag_out : out user_tag_t;
phy_ctrl : out phy_ctrl_t;
col_addr : in col_addr_t;
mode_word : in mode_word_t;
cmd : in sdr_cmd_t;
cmd_we : in STD_LOGIC;
cmd_ack : out STD_LOGIC;
col_addr : in col_addr_t;
mode_word : in mode_word_t;
sdr_cmd_ctrl : out sdr_cmd_lines_t;
sdr_addr : out sdr_addr_t;
sdr_ba : out sdr_ba_t
phy_ctrl : out phy_ctrl_t
);
end sdram_cmd;
@@ -84,15 +79,13 @@ architecture behaviour of sdram_cmd is
begin
u_tag_out <= u_tag_in;
------------------------------------------------------------------------------------------
fsm_sdr_state:
process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
begin
st_sdr_next <= st_sdr;
sdr_cmd_ctrl <= COMMAND(SD_NOP);
phy_ctrl.part.cmd <= COMMAND(SD_NOP);
cc_load_en <= '0';
cc_preset <= TIMING(cmd);
@@ -103,12 +96,12 @@ fsm_sdr_state:
phy_ctrl.drive_en <= '0';
phy_ctrl.we <= '0';
phy_ctrl.utag_we <= '0';
sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1);
phy_ctrl.part.addr <= mode_word(phy_ctrl.part.addr'left downto phy_ctrl.part.addr'right);
phy_ctrl.part.ba <= mode_word(mode_word_t'left downto mode_word_t'left-1);
case st_sdr is
when PWR_DOWN =>
sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
phy_ctrl.part.cmd <= COMMAND(SD_DESELECT);
if enable = '1' then
st_sdr_next <= IDLE;
end if;
@@ -128,7 +121,7 @@ fsm_sdr_state:
cmd_ack <= '1';
cc_load_en <= '1';
cc_preset <= TIMING(cmd);
sdr_cmd_ctrl <= COMMAND(cmd);
phy_ctrl.part.cmd <= COMMAND(cmd);
case cmd is
when SD_PRE =>
st_sdr_next <= PRECHARGE;
@@ -149,19 +142,19 @@ fsm_sdr_state:
burst_load_en <= '1';
cc_load_en <= '1';
cc_preset <= TIMING(cmd);
sdr_cmd_ctrl <= COMMAND(cmd);
phy_ctrl.part.cmd <= COMMAND(cmd);
case cmd is
when SD_PRE =>
st_sdr_next <= PRECHARGE;
when SD_READ =>
phy_ctrl.utag_we <= '1';
st_sdr_next <= READ;
sdr_addr(col_addr_t'range) <= col_addr;
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
when SD_WRITE =>
phy_ctrl.utag_we <= '1';
phy_ctrl.drive_en <= '1';
st_sdr_next <= WRITE;
sdr_addr(col_addr_t'range) <= col_addr;
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
when others => null;
end case;
end if;
@@ -172,10 +165,10 @@ fsm_sdr_state:
phy_ctrl.we <= '1';
if burst_finished = '1' then
if cmd_we = '1' and cmd = SD_WRITE then
sdr_addr(col_addr_t'range) <= col_addr;
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
cmd_ack <= '1';
burst_load_en <= '1';
sdr_cmd_ctrl <= COMMAND(cmd);
phy_ctrl.part.cmd <= COMMAND(cmd);
phy_ctrl.utag_we <= '1';
else
phy_ctrl.drive_en <= '0';
@@ -189,10 +182,10 @@ fsm_sdr_state:
phy_ctrl.re <= '1';
if burst_finished = '1' then
if cmd_we = '1' and cmd = SD_READ then
sdr_addr(col_addr_t'range) <= col_addr;
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
cmd_ack <= '1';
burst_load_en <= '1';
sdr_cmd_ctrl <= COMMAND(cmd);
phy_ctrl.part.cmd <= COMMAND(cmd);
phy_ctrl.utag_we <= '1';
else
cc_load_en <= '1';