diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd index 1c58a02..bebabef 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd @@ -43,16 +43,14 @@ entity sdram_phy is clk_fb : in STD_LOGIC; clk0_out : out STD_LOGIC; rst0_out : out STD_LOGIC; - u_tag_in : in user_tag_t; u_tag_rd : out user_tag_t; u_tag_wr : out user_tag_t; - phy_ctrl : in phy_ctrl_t; - part_ctrl : in part_ctrl_t; - sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_data_vld : out STD_LOGIC; - sdr_data_req_w : out STD_LOGIC; + u_wr_data : in unsigned(SDR_DATA_WIDTH-1 downto 0); + u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); + u_rd_data : out unsigned(SDR_DATA_WIDTH-1 downto 0); + u_rd_data_we : out STD_LOGIC; + u_wr_data_re : out STD_LOGIC; + phy_ctrl : in phy_ctrl_t; part_clk_p : out STD_LOGIC; part_clk_n : out STD_LOGIC; part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); @@ -143,7 +141,7 @@ utag_pipe: u_tag_pipe(i) <= u_tag_pipe(i-1); end loop; if phy_ctrl.utag_we = '1' then - u_tag_pipe(0) <= u_tag_in; + u_tag_pipe(0) <= phy_ctrl.u_tag; end if; end if; end process; @@ -235,8 +233,8 @@ gen_ddr_data_out: Q => ddr_data_w(n), -- 1-bit DDR output C => clk_wr, -- 1-bit clock input CE => '1', -- 1-bit clock enable input - D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_data_w(n), -- 1-bit data input (negative edge) + D1 => u_wr_data(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) + D2 => u_wr_data(n), -- 1-bit data input (negative edge) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); @@ -274,8 +272,8 @@ gen_ddr_dm_out: Q => part_dm(n), -- 1-bit DDR output C => clk_wr, -- 1-bit clock input CE => '1', -- 1-bit clock enable input - D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_dm(n), -- 1-bit data input (negative edge) + D1 => u_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) + D2 => u_dm(n), -- 1-bit data input (negative edge) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); @@ -338,7 +336,7 @@ gen_out_mux_dqs: part_ctrl_reg.addr <= (others=>'0'); part_ctrl_reg.cke <= '0'; else - part_ctrl_reg <= part_ctrl; + part_ctrl_reg <= phy_ctrl.part; end if; end if; end process; @@ -399,18 +397,18 @@ misc_flags_and_data_out: if rst0 = '1' then p := (others => '0'); read_en <= '0'; - sdr_data_vld <= '0'; - sdr_data_req_w <= '0'; + u_rd_data_we <= '0'; + u_wr_data_re <= '0'; else - sdr_data_r <= data_reg_r; + u_rd_data <= data_reg_r; if p(3) = '1' then u_tag_rd <= u_tag_pipe(4); end if; if phy_ctrl.we = '1' then u_tag_wr <= u_tag_pipe(0); end if; - sdr_data_req_w <= phy_ctrl.we; - sdr_data_vld <= p(3); + u_wr_data_re <= phy_ctrl.we; + u_rd_data_we <= p(3); read_en <= p(1); if phy_ctrl.re = '1' then p := p(p'left-1 downto 0) & '1'; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd index ae38d48..048c52e 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd @@ -39,17 +39,12 @@ entity sdram_cmd is rst : in STD_LOGIC; clk : in STD_LOGIC; enable : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - phy_ctrl : out phy_ctrl_t; + col_addr : in col_addr_t; + mode_word : in mode_word_t; cmd : in sdr_cmd_t; cmd_we : in STD_LOGIC; cmd_ack : out STD_LOGIC; - col_addr : in col_addr_t; - mode_word : in mode_word_t; - sdr_cmd_ctrl : out sdr_cmd_lines_t; - sdr_addr : out sdr_addr_t; - sdr_ba : out sdr_ba_t + phy_ctrl : out phy_ctrl_t ); end sdram_cmd; @@ -84,15 +79,13 @@ architecture behaviour of sdram_cmd is begin - u_tag_out <= u_tag_in; - ------------------------------------------------------------------------------------------ fsm_sdr_state: process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr) begin st_sdr_next <= st_sdr; - sdr_cmd_ctrl <= COMMAND(SD_NOP); + phy_ctrl.part.cmd <= COMMAND(SD_NOP); cc_load_en <= '0'; cc_preset <= TIMING(cmd); @@ -103,12 +96,12 @@ fsm_sdr_state: phy_ctrl.drive_en <= '0'; phy_ctrl.we <= '0'; phy_ctrl.utag_we <= '0'; - sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right); - sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); + phy_ctrl.part.addr <= mode_word(phy_ctrl.part.addr'left downto phy_ctrl.part.addr'right); + phy_ctrl.part.ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); case st_sdr is when PWR_DOWN => - sdr_cmd_ctrl <= COMMAND(SD_DESELECT); + phy_ctrl.part.cmd <= COMMAND(SD_DESELECT); if enable = '1' then st_sdr_next <= IDLE; end if; @@ -128,7 +121,7 @@ fsm_sdr_state: cmd_ack <= '1'; cc_load_en <= '1'; cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); + phy_ctrl.part.cmd <= COMMAND(cmd); case cmd is when SD_PRE => st_sdr_next <= PRECHARGE; @@ -149,19 +142,19 @@ fsm_sdr_state: burst_load_en <= '1'; cc_load_en <= '1'; cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); + phy_ctrl.part.cmd <= COMMAND(cmd); case cmd is when SD_PRE => st_sdr_next <= PRECHARGE; when SD_READ => phy_ctrl.utag_we <= '1'; st_sdr_next <= READ; - sdr_addr(col_addr_t'range) <= col_addr; + phy_ctrl.part.addr(col_addr_t'range) <= col_addr; when SD_WRITE => phy_ctrl.utag_we <= '1'; phy_ctrl.drive_en <= '1'; st_sdr_next <= WRITE; - sdr_addr(col_addr_t'range) <= col_addr; + phy_ctrl.part.addr(col_addr_t'range) <= col_addr; when others => null; end case; end if; @@ -172,10 +165,10 @@ fsm_sdr_state: phy_ctrl.we <= '1'; if burst_finished = '1' then if cmd_we = '1' and cmd = SD_WRITE then - sdr_addr(col_addr_t'range) <= col_addr; + phy_ctrl.part.addr(col_addr_t'range) <= col_addr; cmd_ack <= '1'; burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); + phy_ctrl.part.cmd <= COMMAND(cmd); phy_ctrl.utag_we <= '1'; else phy_ctrl.drive_en <= '0'; @@ -189,10 +182,10 @@ fsm_sdr_state: phy_ctrl.re <= '1'; if burst_finished = '1' then if cmd_we = '1' and cmd = SD_READ then - sdr_addr(col_addr_t'range) <= col_addr; + phy_ctrl.part.addr(col_addr_t'range) <= col_addr; cmd_ack <= '1'; burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); + phy_ctrl.part.cmd <= COMMAND(cmd); phy_ctrl.utag_we <= '1'; else cc_load_en <= '1'; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd index 286dd70..47c4352 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd @@ -87,8 +87,8 @@ architecture struct of sdram_ctrl_frontend64_wb is signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; + signal u_rd_data_we : std_logic; + signal u_wr_data_re : std_logic; signal rdy : std_logic; constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; @@ -222,8 +222,8 @@ begin sdram_rst_out => SDRAM_RST0, -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, + u_rd_data_we => u_rd_data_we, + u_wr_data_re => u_wr_data_re, u_tag_in => u_tag_in, u_tag_rd => u_tag_rd, u_tag_wr => u_tag_wr, @@ -231,8 +231,8 @@ begin u_addr => u_addr, u_cmd => u_cmd, u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, + u_wr_data => u_data_w, + u_rd_data => u_data_r, u_dm => u_dm_wr_in, -- SDRAM signals @@ -271,10 +271,10 @@ begin u_tag_in <= tag_fifo_out; u_data_w <= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when u_tag_wr(0) = '1' else write_fifo_data_out(63 downto 0); - write_fifo_re <= u_req_wr and (not write_fifo_empty); + write_fifo_re <= u_wr_data_re and (not write_fifo_empty); cat_fifo_re <= u_cmd_we; read_fifo_re <= (not read_fifo_empty) and MRDY_I; - read_fifo_we <= u_data_vld; + read_fifo_we <= u_rd_data_we; read_fifo_data_in <= (u_data_r(31 downto 0) & u_data_r(63 downto 32)) when u_tag_rd(0) = '1' else u_data_r(63 downto 0); end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd index 51bc89a..d4d4138 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd @@ -87,8 +87,8 @@ architecture struct of sdram_ctrl_frontend_wb is signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; + signal u_rd_data_we : std_logic; + signal u_wr_data_re : std_logic; signal rdy : std_logic; constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; @@ -222,8 +222,8 @@ begin sdram_rst_out => SDRAM_RST0, -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, + u_rd_data_we => u_rd_data_we, + u_wr_data_re => u_wr_data_re, u_tag_in => u_tag_in, u_tag_rd => u_tag_rd, u_tag_wr => u_tag_wr, @@ -231,8 +231,8 @@ begin u_addr => u_addr, u_cmd => u_cmd, u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, + u_wr_data => u_data_w, + u_rd_data => u_data_r, u_dm => u_dm_wr_in, -- SDRAM signals @@ -271,10 +271,10 @@ begin u_tag_in <= tag_fifo_out; u_data_w <= write_fifo_data_out & write_fifo_data_out; - write_fifo_re <= u_req_wr and (not write_fifo_empty); + write_fifo_re <= u_wr_data_re and (not write_fifo_empty); cat_fifo_re <= u_cmd_we; read_fifo_re <= (not read_fifo_empty) and MRDY_I; - read_fifo_we <= u_data_vld; + read_fifo_we <= u_rd_data_we; read_fifo_data_in <= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32); end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd index ee53b66..541f98f 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd @@ -47,18 +47,18 @@ entity sdram_ctrl_top is sdram_rst_out : out STD_LOGIC; -- User interface - u_data_vld : out STD_LOGIC; - u_data_req_w : out STD_LOGIC; + u_rd_data_we : out STD_LOGIC; + u_wr_data_re : out STD_LOGIC; u_busy : out STD_LOGIC; + u_cmd : in user_cmd_t; + u_cmd_we : in STD_LOGIC; + u_addr : in user_addr_t; u_tag_in : in user_tag_t; u_tag_rd : out user_tag_t; u_tag_wr : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); + u_wr_data : in unsigned(SDR_DATA_WIDTH-1 downto 0); u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0); + u_rd_data : out unsigned(SDR_DATA_WIDTH-1 downto 0); -- SDRAM signals sd_clk_p : out STD_LOGIC; @@ -82,23 +82,15 @@ architecture rtl of sdram_ctrl_top is signal sdram_clk0 : std_logic; signal sdram_rst0 : std_logic; - signal phy_ctrl : phy_ctrl_t; - signal u_tag : user_tag_t; signal sd_cmd_in : sdr_cmd_t; signal sd_cmd : sdr_cmd_t; signal sd_cmd_we : std_logic; - signal cmd_ctrl : sdr_cmd_lines_t; signal cke : std_logic; - signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - -- Clock generator - - signal part_ctrl : part_ctrl_t; + signal phy_ctrl : phy_ctrl_t; -- SD command FIFO - constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); @@ -122,11 +114,9 @@ begin sdram_rst_out <= sdram_rst0; --------------------------------- - part_ctrl.cmd <= cmd_ctrl; - part_ctrl.ba <= ba; - part_ctrl.addr <= addr; - part_ctrl.cke <= cke; - + phy_ctrl.part.cke <= cke; + phy_ctrl.u_tag <= sd_tag_fifo_out; + --------------------------------- sd_cmd_we <= not cmd_fifo_empty; cmd_fifo_in <= to_unsigned(sd_cmd_in, 4); @@ -192,18 +182,13 @@ begin ( rst => sdram_rst0, clk => sdram_clk0, - u_tag_in => sd_tag_fifo_out, - u_tag_out => u_tag, phy_ctrl => phy_ctrl, enable => cke, cmd => sd_cmd, cmd_we => sd_cmd_we, cmd_ack => cmd_fifo_re, - sdr_cmd_ctrl => cmd_ctrl, col_addr => sd_col_fifo_out, - mode_word => sd_mode_fifo_out, - sdr_ba => ba, - sdr_addr => addr + mode_word => sd_mode_fifo_out ); -- DDR phy @@ -219,16 +204,14 @@ begin clk_fb => sdram_clk_fb, clk0_out => sdram_clk0, rst0_out => sdram_rst0, - u_tag_in => u_tag, u_tag_rd => u_tag_rd, u_tag_wr => u_tag_wr, + u_wr_data_re => u_wr_data_re, + u_wr_data => u_wr_data, + u_dm => u_dm, + u_rd_data => u_rd_data, + u_rd_data_we => u_rd_data_we, phy_ctrl => phy_ctrl, - part_ctrl => part_ctrl, - sdr_data_req_w => u_data_req_w, - sdr_data_w => u_data_wr, - sdr_dm => u_dm, - sdr_data_r => u_data_rd, - sdr_data_vld => u_data_vld, part_clk_p => sd_clk_p, part_clk_n => sd_clk_n, part_addr => sd_addr, diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd index 5520b28..e52e16e 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd @@ -68,14 +68,6 @@ package sdram_types is subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); subtype col_addr_t is unsigned(8 downto 0); - type phy_ctrl_t is - record - drive_en : std_logic; - re : std_logic; - we : std_logic; - utag_we : std_logic; - end record phy_ctrl_t; - type sdr_cmd_lines_t is record cs_n : std_logic; @@ -92,6 +84,16 @@ package sdram_types is cke : std_logic; end record part_ctrl_t; + type phy_ctrl_t is + record + drive_en : std_logic; + re : std_logic; + we : std_logic; + utag_we : std_logic; + part : part_ctrl_t; + u_tag : user_tag_t; + end record phy_ctrl_t; + type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t; constant COMMAND : part_cmd_array_t := -- command cs_n ras_qn cas_qn we_qn