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Force VCD

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This commit is contained in:
jens
2022-06-30 22:54:19 +02:00
parent bcc18b973c
commit 87282eccec
2 changed files with 4 additions and 2 deletions
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lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make
+2 -1
View File
@@ -27,8 +27,9 @@ SRCS += $(MOD_PATH)/src/tb_ctrl_ddr_wb32.vhd
TARGET := tb_ctrl_ddr_wb32
ENTITY := tb_ctrl_ddr_wb32
RUN_TIME := 200us
WAVE_FORMAT := vcd
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
include $(VHDL_HOME)/make/ghdl.mk
lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make
+2 -1
View File
@@ -26,8 +26,9 @@ SRCS += $(MOD_PATH)/src/tb_ctrl_ddr_wb64.vhd
TARGET := tb_ctrl_ddr_wb64
ENTITY := tb_ctrl_ddr_wb64
RUN_TIME := 200us
WAVE_FORMAT := vcd
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
include $(VHDL_HOME)/make/ghdl.mk