From 87282ecceccc0367648065667b62533cd76f6d4c Mon Sep 17 00:00:00 2001 From: jens Date: Thu, 30 Jun 2022 22:54:19 +0200 Subject: [PATCH] Force VCD --- lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make | 3 ++- lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make index 03afc29..b4bb269 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make +++ b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make @@ -27,8 +27,9 @@ SRCS += $(MOD_PATH)/src/tb_ctrl_ddr_wb32.vhd TARGET := tb_ctrl_ddr_wb32 ENTITY := tb_ctrl_ddr_wb32 RUN_TIME := 200us +WAVE_FORMAT := vcd -GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit +GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit include $(VHDL_HOME)/make/ghdl.mk diff --git a/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make index 324a42c..476abb9 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make +++ b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make @@ -26,8 +26,9 @@ SRCS += $(MOD_PATH)/src/tb_ctrl_ddr_wb64.vhd TARGET := tb_ctrl_ddr_wb64 ENTITY := tb_ctrl_ddr_wb64 RUN_TIME := 200us +WAVE_FORMAT := vcd -GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit +GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit include $(VHDL_HOME)/make/ghdl.mk