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- fixed full write

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1610 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-31 09:25:35 +00:00
parent c922fbe961
commit 83373bbae5
1 changed files with 4 additions and 2 deletions
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lib/FIFO/src/reg_stage.vhd
+4 -2
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@@ -49,10 +49,12 @@ architecture Behavioral of reg_stage is
signal dvld : std_logic; signal dvld : std_logic;
signal fct : std_logic; signal fct : std_logic;
signal full_s : std_logic;
begin begin
full <= dvld and not re; full <= full_s;
full_s <= dvld and not re;
vld_dout <= dvld; vld_dout <= dvld;
fct <= we or (dvld and not re); fct <= we or (dvld and not re);
@@ -72,7 +74,7 @@ proc_data_reg:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if we = '1' then if we = '1' and full_s = '0' then
dout <= din; dout <= din;
end if; end if;
end if; end if;