From 83373bbae580aae1e507e9f3681769908896ebe5 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 31 Mar 2021 09:25:35 +0000 Subject: [PATCH] - fixed full write git-svn-id: http://moon:8086/svn/vhdl/trunk@1610 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/FIFO/src/reg_stage.vhd | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/FIFO/src/reg_stage.vhd b/lib/FIFO/src/reg_stage.vhd index c011fb6..607c83d 100644 --- a/lib/FIFO/src/reg_stage.vhd +++ b/lib/FIFO/src/reg_stage.vhd @@ -49,10 +49,12 @@ architecture Behavioral of reg_stage is signal dvld : std_logic; signal fct : std_logic; + signal full_s : std_logic; begin - full <= dvld and not re; + full <= full_s; + full_s <= dvld and not re; vld_dout <= dvld; fct <= we or (dvld and not re); @@ -72,7 +74,7 @@ proc_data_reg: process(clk) begin if rising_edge(clk) then - if we = '1' then + if we = '1' and full_s = '0' then dout <= din; end if; end if;