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- VGA backend: use synchronous resets

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- VGA backend: proc_vga_color_out: keep color signals stable - reduce noise


git-svn-id: http://moon:8086/svn/vhdl/trunk@1595 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-30 07:20:00 +00:00
parent 24e5cb75cb
commit 83315b4c17
1 changed files with 23 additions and 20 deletions
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lib/VGA_ctrl/src/vga_backend.vhd
+9 -6
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@@ -116,12 +116,12 @@ inst_vga_timing: entity work.vga_timing
--------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------
proc_vga_start: proc_vga_start:
process (vga_rst, vga_clk) process (vga_clk)
begin begin
if rising_edge(vga_clk) then
if vga_rst = '1' then if vga_rst = '1' then
scan_enable <= '0'; scan_enable <= '0';
elsif rising_edge(vga_clk) then elsif vsync = '1' then
if vsync = '1' then
if ctrl_scan_en = '1' then if ctrl_scan_en = '1' then
scan_enable <= '1'; scan_enable <= '1';
else else
@@ -137,10 +137,11 @@ inst_vga_timing: entity work.vga_timing
variable color : color_t; variable color : color_t;
begin begin
if rising_edge(vga_clk) then if rising_edge(vga_clk) then
if vga_rst = '1' then
vga_red <= X"00"; vga_red <= X"00";
vga_green <= X"00"; vga_green <= X"00";
vga_blue <= X"00"; vga_blue <= X"00";
if is_scan = '1' then elsif is_scan = '1' then
for i in 0 to VGA_NUM_CH-1 loop for i in 0 to VGA_NUM_CH-1 loop
color := color_in(i); color := color_in(i);
if color_en(i) = '1' then if color_en(i) = '1' then
@@ -155,21 +156,23 @@ inst_vga_timing: entity work.vga_timing
--------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------
proc_vga_sync_out: proc_vga_sync_out:
process (vga_rst, vga_clk) process (vga_clk)
variable hsync_r : std_logic; variable hsync_r : std_logic;
variable vsync_r : std_logic; variable vsync_r : std_logic;
begin begin
if rising_edge(vga_clk) then
if vga_rst = '1' then if vga_rst = '1' then
vga_hsync <= tsvga.ts_h.sync_polarity; vga_hsync <= tsvga.ts_h.sync_polarity;
vga_vsync <= tsvga.ts_v.sync_polarity; vga_vsync <= tsvga.ts_v.sync_polarity;
hsync_r := tsvga.ts_h.sync_polarity; hsync_r := tsvga.ts_h.sync_polarity;
vsync_r := tsvga.ts_v.sync_polarity; vsync_r := tsvga.ts_v.sync_polarity;
elsif rising_edge(vga_clk) then else
vga_hsync <= hsync_r; vga_hsync <= hsync_r;
vga_vsync <= vsync_r; vga_vsync <= vsync_r;
hsync_r := hsync xor (not tsvga.ts_h.sync_polarity); hsync_r := hsync xor (not tsvga.ts_h.sync_polarity);
vsync_r := vsync xor (not tsvga.ts_v.sync_polarity); vsync_r := vsync xor (not tsvga.ts_v.sync_polarity);
end if; end if;
end if;
end process; end process;
end Behavioral; end Behavioral;