From 83315b4c17a46dd77d6e4c7d6a60b4135d865709 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 30 Mar 2021 07:20:00 +0000 Subject: [PATCH] - VGA backend: use synchronous resets - VGA backend: proc_vga_color_out: keep color signals stable - reduce noise git-svn-id: http://moon:8086/svn/vhdl/trunk@1595 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/VGA_ctrl/src/vga_backend.vhd | 43 +++++++++++++++++--------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/lib/VGA_ctrl/src/vga_backend.vhd b/lib/VGA_ctrl/src/vga_backend.vhd index cfc3668..6374c06 100644 --- a/lib/VGA_ctrl/src/vga_backend.vhd +++ b/lib/VGA_ctrl/src/vga_backend.vhd @@ -116,12 +116,12 @@ inst_vga_timing: entity work.vga_timing --------------------------------------------------------------------------------------------- proc_vga_start: - process (vga_rst, vga_clk) + process (vga_clk) begin - if vga_rst = '1' then - scan_enable <= '0'; - elsif rising_edge(vga_clk) then - if vsync = '1' then + if rising_edge(vga_clk) then + if vga_rst = '1' then + scan_enable <= '0'; + elsif vsync = '1' then if ctrl_scan_en = '1' then scan_enable <= '1'; else @@ -137,10 +137,11 @@ inst_vga_timing: entity work.vga_timing variable color : color_t; begin if rising_edge(vga_clk) then - vga_red <= X"00"; - vga_green <= X"00"; - vga_blue <= X"00"; - if is_scan = '1' then + if vga_rst = '1' then + vga_red <= X"00"; + vga_green <= X"00"; + vga_blue <= X"00"; + elsif is_scan = '1' then for i in 0 to VGA_NUM_CH-1 loop color := color_in(i); if color_en(i) = '1' then @@ -155,20 +156,22 @@ inst_vga_timing: entity work.vga_timing --------------------------------------------------------------------------------------------- proc_vga_sync_out: - process (vga_rst, vga_clk) + process (vga_clk) variable hsync_r : std_logic; variable vsync_r : std_logic; begin - if vga_rst = '1' then - vga_hsync <= tsvga.ts_h.sync_polarity; - vga_vsync <= tsvga.ts_v.sync_polarity; - hsync_r := tsvga.ts_h.sync_polarity; - vsync_r := tsvga.ts_v.sync_polarity; - elsif rising_edge(vga_clk) then - vga_hsync <= hsync_r; - vga_vsync <= vsync_r; - hsync_r := hsync xor (not tsvga.ts_h.sync_polarity); - vsync_r := vsync xor (not tsvga.ts_v.sync_polarity); + if rising_edge(vga_clk) then + if vga_rst = '1' then + vga_hsync <= tsvga.ts_h.sync_polarity; + vga_vsync <= tsvga.ts_v.sync_polarity; + hsync_r := tsvga.ts_h.sync_polarity; + vsync_r := tsvga.ts_v.sync_polarity; + else + vga_hsync <= hsync_r; + vga_vsync <= vsync_r; + hsync_r := hsync xor (not tsvga.ts_h.sync_polarity); + vsync_r := vsync xor (not tsvga.ts_v.sync_polarity); + end if; end if; end process;