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git-svn-id: http://moon:8086/svn/vhdl/trunk@747 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-09 12:10:10 +00:00
parent e162dd8798
commit 819028cd9b
4 changed files with 1122 additions and 1297 deletions
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projects/mips_sys/ise101/mips_sys/mips_sys.syr
+169 -160
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@@ -4,13 +4,13 @@ Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: mips_sys.prj
@@ -128,6 +128,7 @@ Architecture behavioral of Entity fifo_async_ctrl is up to date.
Compiling vhdl file "W:/vhdl/lib/misc/dpram_1w1r.vhd" in Library work.
Architecture behavioral of Entity dpram_1w1r is up to date.
Compiling vhdl file "W:/vhdl/lib/misc/utils_pkg.vhd" in Library work.
WARNING:HDLParsers:3534 - "W:/vhdl/lib/misc/utils_pkg.vhd" Line 155. In the function f_correct, not all control paths contain a return statement.
Architecture utils_pkg of Entity utils_pkg is up to date.
Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd" in Library work.
Architecture behavioral of Entity ac_in is up to date.
@@ -156,7 +157,8 @@ Architecture low_level_definition of Entity kcuart_tx is up to date.
Compiling vhdl file "W:/vhdl/lib/ps2_port/src/debounce.vhd" in Library work.
Architecture behavioral of Entity debounce is up to date.
Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" in Library work.
Architecture behavioral of Entity ps2_core is up to date.
Entity <ps2_core> compiled.
Entity <ps2_core> (Architecture <behavioral>) compiled.
Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync.vhd" in Library work.
Architecture behavioral of Entity fifo_sync is up to date.
Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd" in Library work.
@@ -174,7 +176,8 @@ Architecture macro_level_definition of Entity uart_rx is up to date.
Compiling vhdl file "W:/vhdl/lib/misc/async_types.vhd" in Library work.
Architecture async_types of Entity async_types is up to date.
Compiling vhdl file "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd" in Library work.
Architecture data of Entity rom is up to date.
Entity <rom> compiled.
Entity <rom> (Architecture <data>) compiled.
Compiling vhdl file "W:/vhdl/lib/CPUs/MIPS/src/core/mips_types.vhd" in Library work.
Architecture mips_types of Entity mips_types is up to date.
Compiling vhdl file "W:/vhdl/projects/mips_sys/src/async_defs.vhd" in Library work.
@@ -183,7 +186,8 @@ Architecture behavior of Entity rom_wb is up to date.
Compiling vhdl file "W:/vhdl/lib/misc/lcd_port.vhd" in Library work.
Architecture behavioral of Entity lcd_port is up to date.
Compiling vhdl file "W:/vhdl/lib/misc/gpio_wb.vhd" in Library work.
Architecture behavior of Entity gpio_wb is up to date.
Entity <gpio_wb> compiled.
Entity <gpio_wb> (Architecture <behavior>) compiled.
Compiling vhdl file "W:/vhdl/lib/misc/async_port_wb.vhd" in Library work.
Architecture behavioral of Entity async_port_wb is up to date.
Compiling vhdl file "W:/vhdl/lib/uart/uart_wb.vhd" in Library work.
@@ -201,17 +205,15 @@ Architecture behavior of Entity ps2_wb is up to date.
Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd" in Library work.
Architecture behavioral of Entity ps2_phy is up to date.
Compiling vhdl file "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" in Library work.
Entity <mips_sys> compiled.
Entity <mips_sys> (Architecture <behavior>) compiled.
Architecture behavior of Entity mips_sys is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <mips_sys> in library <work> (architecture <behavior>) with generics.
ddr_frequency_hz = 100000000
ddr_phaseshift = 0
sys_freq = 100000000
sys_freq_in = 100000000
sdram_phaseshift = 0
sys_freq = 100.000000
sys_freq_in = 100.000000
tsvga = (f_pxl_clk => 40000000
nfps => 60
ts_h => (ncyc_scan => 800
@@ -229,7 +231,8 @@ Analyzing hierarchy for entity <rom_wb> in library <work> (architecture <behavio
Analyzing hierarchy for entity <lcd_port> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <gpio_wb> in library <work> (architecture <behavior>).
Analyzing hierarchy for entity <gpio_wb> in library <work> (architecture <behavior>) with generics.
f_sysclk = 100.000000
Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <behavioral>) with generics.
addr_width = 25
@@ -249,7 +252,7 @@ Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <
pol_rst => '0')
byte_sel_width = 1
data_width = 32
f_sysclk_hz = 100000000
f_sysclk = 100.000000
Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <behavioral>) with generics.
addr_width = 4
@@ -269,21 +272,25 @@ Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <
pol_rst => '0')
byte_sel_width = 1
data_width = 16
f_sysclk_hz = 100000000
f_sysclk = 100.000000
Analyzing hierarchy for entity <uart_wb> in library <work> (architecture <behavior>).
Analyzing hierarchy for entity <clockgen> in library <work> (architecture <tech>) with generics.
clk_in_freq_hz = 100000000
clk_in_freq = 100.000000
sdr0_clk_out_phaseshift = 0
sdr1_clk_out_phaseshift = 0
sys_clk_out_freq_hz = 100000000
vga_clk_out_freq_hz = 40000000
sys_clk_out_freq = 100.000000
vga_clk_out_freq = 40.000000
WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored.
Analyzing hierarchy for entity <sdram_ctrl_frontend64_wb> in library <work> (architecture <struct>) with generics.
BL = 2
f_sdrclk_hz = 100000000
f_sysclk_hz = 100000000
f_sdrclk = 100.000000
f_sysclk = 100.000000
fifo_depth = 5
Analyzing hierarchy for entity <vga_frontend64> in library <work> (architecture <behavioral>) with generics.
@@ -307,7 +314,7 @@ Analyzing hierarchy for entity <ac97_wb> in library <work> (architecture <behavi
fifo_depth = 8
Analyzing hierarchy for entity <ps2_wb> in library <work> (architecture <behavior>) with generics.
f_sys_clk_hz = 100000000
f_sys_clk = 100.000000
Analyzing hierarchy for entity <ps2_phy> in library <work> (architecture <Behavioral>).
@@ -337,8 +344,8 @@ Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Beh
Analyzing hierarchy for entity <sdram_ctrl_top> in library <work> (architecture <rtl>) with generics.
BL = 2
f_sdrclk_hz = 100000000
f_sysclk_hz = 100000000
f_sdrclk = 100.000000
f_sysclk = 100.000000
fifo_depth = 5
Analyzing hierarchy for entity <vga_backend> in library <work> (architecture <Behavioral>) with generics.
@@ -406,7 +413,7 @@ Analyzing hierarchy for entity <fifo_sync> in library <work> (architecture <Beha
Analyzing hierarchy for entity <ac_io> in library <work> (architecture <Behavioral>).
Analyzing hierarchy for entity <ps2_core> in library <work> (architecture <Behavioral>) with generics.
f_sys_clk_hz = 100000000
f_sys_clk = 100.000000
Analyzing hierarchy for entity <debounce> in library <work> (architecture <behavioral>) with generics.
ncyc_latency = 8
@@ -441,7 +448,7 @@ Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Beh
Analyzing hierarchy for entity <sdram_ctrl> in library <work> (architecture <behaviour>) with generics.
BL = 2
f_sysclk_hz = 100000000
f_sysclk = 100.000000
Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Behavioral>) with generics.
addr_width = 5
@@ -451,7 +458,7 @@ Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Beh
Analyzing hierarchy for entity <sdram_cmd> in library <work> (architecture <behaviour>) with generics.
BL = 2
f_sdrclk_hz = 100000000
f_sdrclk = 100.000000
Analyzing hierarchy for entity <ddr_phy> in library <work> (architecture <tech>).
@@ -576,10 +583,9 @@ WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 333: attribute on insta
* HDL Analysis *
=========================================================================
Analyzing generic Entity <mips_sys> in library <work> (Architecture <behavior>).
ddr_frequency_hz = 100000000
ddr_phaseshift = 0
sys_freq = 100000000
sys_freq_in = 100000000
sdram_phaseshift = 0
sys_freq = 100.000000
sys_freq_in = 100.000000
tsvga = (f_pxl_clk => 40000000
nfps => 60
ts_h => (ncyc_scan => 800
@@ -597,12 +603,12 @@ Analyzing generic Entity <mips_sys> in library <work> (Architecture <behavior>).
Set user-defined property "KEEP = TRUE" for signal <vga_clk>.
Set user-defined property "KEEP = TRUE" for signal <CLK_O>.
Set user-defined property "KEEP = TRUE" for signal <RST_O>.
WARNING:Xst:2211 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 674: Instantiating black box module <mips_top>.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 711: Unconnected output port 'dout' of component 'lcd_port'.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 748: Unconnected output port 'async_be' of component 'async_port_wb'.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 781: Unconnected output port 'async_be' of component 'async_port_wb'.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 781: Unconnected output port 'async_rst' of component 'async_port_wb'.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 855: Unconnected output port 'sdr1_clk0_out' of component 'clockgen'.
WARNING:Xst:2211 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 678: Instantiating black box module <mips_top>.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 715: Unconnected output port 'dout' of component 'lcd_port'.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 756: Unconnected output port 'async_be' of component 'async_port_wb'.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 789: Unconnected output port 'async_be' of component 'async_port_wb'.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 789: Unconnected output port 'async_rst' of component 'async_port_wb'.
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 863: Unconnected output port 'sdr1_clk0_out' of component 'clockgen'.
Entity <mips_sys> analyzed. Unit <mips_sys> generated.
Analyzing Entity <rom_wb> in library <work> (Architecture <behavior>).
@@ -615,7 +621,8 @@ Entity <rom> analyzed. Unit <rom> generated.
Analyzing Entity <lcd_port> in library <work> (Architecture <behavioral>).
Entity <lcd_port> analyzed. Unit <lcd_port> generated.
Analyzing Entity <gpio_wb> in library <work> (Architecture <behavior>).
Analyzing generic Entity <gpio_wb> in library <work> (Architecture <behavior>).
f_sysclk = 100.000000
Entity <gpio_wb> analyzed. Unit <gpio_wb> generated.
Analyzing generic Entity <async_port_wb.1> in library <work> (Architecture <behavioral>).
@@ -636,7 +643,7 @@ Analyzing generic Entity <async_port_wb.1> in library <work> (Architecture <beha
pol_rst => '0')
byte_sel_width = 1
data_width = 32
f_sysclk_hz = 100000000
f_sysclk = 100.000000
Entity <async_port_wb.1> analyzed. Unit <async_port_wb.1> generated.
Analyzing generic Entity <async_port_wb.2> in library <work> (Architecture <behavioral>).
@@ -657,7 +664,7 @@ Analyzing generic Entity <async_port_wb.2> in library <work> (Architecture <beha
pol_rst => '0')
byte_sel_width = 1
data_width = 16
f_sysclk_hz = 100000000
f_sysclk = 100.000000
Entity <async_port_wb.2> analyzed. Unit <async_port_wb.2> generated.
Analyzing Entity <uart_wb> in library <work> (Architecture <behavior>).
@@ -786,11 +793,11 @@ Analyzing Entity <kcuart_rx> in library <work> (Architecture <low_level_definiti
Entity <kcuart_rx> analyzed. Unit <kcuart_rx> generated.
Analyzing generic Entity <clockgen> in library <work> (Architecture <tech>).
clk_in_freq_hz = 100000000
clk_in_freq = 100.000000
sdr0_clk_out_phaseshift = 0
sdr1_clk_out_phaseshift = 0
sys_clk_out_freq_hz = 100000000
vga_clk_out_freq_hz = 40000000
sys_clk_out_freq = 100.000000
vga_clk_out_freq = 40.000000
Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
Set user-defined property "CLKFX_DIVIDE = 5" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
Set user-defined property "CLKFX_MULTIPLY = 2" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
@@ -861,8 +868,8 @@ Entity <clockgen> analyzed. Unit <clockgen> generated.
Analyzing generic Entity <sdram_ctrl_frontend64_wb> in library <work> (Architecture <struct>).
BL = 2
f_sdrclk_hz = 100000000
f_sysclk_hz = 100000000
f_sdrclk = 100.000000
f_sysclk = 100.000000
fifo_depth = 5
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_afull' of component 'fifo_sync'.
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_aempty' of component 'fifo_sync'.
@@ -927,8 +934,8 @@ Entity <dpram_1w1r.3> analyzed. Unit <dpram_1w1r.3> generated.
Analyzing generic Entity <sdram_ctrl_top> in library <work> (Architecture <rtl>).
BL = 2
f_sdrclk_hz = 100000000
f_sysclk_hz = 100000000
f_sdrclk = 100.000000
f_sysclk = 100.000000
fifo_depth = 5
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_afull' of component 'fifo_async'.
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_aempty' of component 'fifo_async'.
@@ -936,7 +943,7 @@ Entity <sdram_ctrl_top> analyzed. Unit <sdram_ctrl_top> generated.
Analyzing generic Entity <sdram_ctrl> in library <work> (Architecture <behaviour>).
BL = 2
f_sysclk_hz = 100000000
f_sysclk = 100.000000
Entity <sdram_ctrl> analyzed. Unit <sdram_ctrl> generated.
Analyzing generic Entity <fifo_async.4> in library <work> (Architecture <Behavioral>).
@@ -953,7 +960,7 @@ Entity <dpram_1w1r.9> analyzed. Unit <dpram_1w1r.9> generated.
Analyzing generic Entity <sdram_cmd> in library <work> (Architecture <behaviour>).
BL = 2
f_sdrclk_hz = 100000000
f_sdrclk = 100.000000
Entity <sdram_cmd> analyzed. Unit <sdram_cmd> generated.
Analyzing Entity <ddr_phy> in library <work> (Architecture <tech>).
@@ -1419,7 +1426,7 @@ WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" line 128: Index va
Entity <ac_out> analyzed. Unit <ac_out> generated.
Analyzing generic Entity <ps2_wb> in library <work> (Architecture <behavior>).
f_sys_clk_hz = 100000000
f_sys_clk = 100.000000
INFO:Xst:2679 - Register <DAT_O<31>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <DAT_O<30>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <DAT_O<29>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
@@ -1439,7 +1446,7 @@ INFO:Xst:2679 - Register <DAT_O<16>> in unit <ps2_wb> has a constant value of 0
Entity <ps2_wb> analyzed. Unit <ps2_wb> generated.
Analyzing generic Entity <ps2_core> in library <work> (Architecture <Behavioral>).
f_sys_clk_hz = 100000000
f_sys_clk = 100.000000
WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 191: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<sipo_reg>
WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 204: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
@@ -1500,10 +1507,10 @@ WARNING:Xst:1780 - Signal <cnt_sec_preset> is never used or assigned. This uncon
Found 1-bit register for signal <ACK_O>.
Found 32-bit up counter for signal <cnt_sec>.
Found 1-bit register for signal <cnt_sec_en>.
Found 32-bit comparator less for signal <cnt_sec_en$cmp_lt0000> created at line 254.
Found 32-bit comparator less for signal <cnt_sec_en$cmp_lt0000> created at line 259.
Found 1-bit register for signal <cnt_sec_we>.
Found 32-bit up counter for signal <cnt_usec>.
Found 32-bit comparator greatequal for signal <cnt_usec$cmp_ge0000> created at line 254.
Found 32-bit comparator greatequal for signal <cnt_usec$cmp_ge0000> created at line 259.
Found 1-bit register for signal <cnt_usec_en>.
Found 1-bit register for signal <cnt_usec_we>.
Found 32-bit register for signal <gpi0_reg>.
@@ -1512,20 +1519,20 @@ WARNING:Xst:1780 - Signal <cnt_sec_preset> is never used or assigned. This uncon
Found 32-bit register for signal <gpo1_reg>.
Found 32-bit register for signal <reg_data_wr>.
Found 7-bit up counter for signal <tick_usec>.
Found 7-bit comparator greatequal for signal <tick_usec$cmp_ge0000> created at line 236.
Found 7-bit comparator greatequal for signal <tick_usec$cmp_ge0000> created at line 241.
Found 64-bit register for signal <timer_cmp>.
Found 2-bit register for signal <timer_cmp_we>.
Found 32-bit up counter for signal <timer_cnt>.
Found 32-bit comparator greatequal for signal <timer_cnt_0$cmp_ge0000> created at line 291.
Found 32-bit comparator greatequal for signal <timer_cnt_1$cmp_ge0000> created at line 291.
Found 32-bit comparator greatequal for signal <timer_cnt_0$cmp_ge0000> created at line 296.
Found 32-bit comparator greatequal for signal <timer_cnt_1$cmp_ge0000> created at line 296.
Found 2-bit register for signal <timer_cnt_we>.
Found 2-bit register for signal <timer_en>.
Found 2-bit register for signal <timer_inten>.
Found 2-bit register for signal <timer_irq>.
Found 2-bit register for signal <timer_irq_ack>.
Found 2-bit register for signal <timer_ovl>.
Found 32-bit comparator less for signal <timer_ovl_0$cmp_lt0000> created at line 291.
Found 32-bit comparator less for signal <timer_ovl_1$cmp_lt0000> created at line 291.
Found 32-bit comparator less for signal <timer_ovl_0$cmp_lt0000> created at line 296.
Found 32-bit comparator less for signal <timer_ovl_1$cmp_lt0000> created at line 296.
Summary:
inferred 5 Counter(s).
inferred 339 D-type flip-flop(s).
@@ -1541,12 +1548,13 @@ WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and
WARNING:Xst:646 - Signal <page_mode_en_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SEL_I_r<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ADDR_I_r<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:1799 - State leadout is never reached in FSM <s>.
Found finite state machine <FSM_0> for signal <s>.
-----------------------------------------------------------------------
| States | 7 |
| Transitions | 15 |
| Inputs | 3 |
| Outputs | 6 |
| States | 6 |
| Transitions | 14 |
| Inputs | 4 |
| Outputs | 5 |
| Clock | CLK_I (rising_edge) |
| Reset | RST_I (positive) |
| Reset type | synchronous |
@@ -1565,7 +1573,7 @@ WARNING:Xst:646 - Signal <ADDR_I_r<3:0>> is assigned but never used. This unconn
Found 1-bit register for signal <async_cs>.
Found 1-bit register for signal <async_rd>.
Found 25-bit register for signal <ADDR_I_r>.
Found 4-bit down counter for signal <cycle_cnt>.
Found 5-bit down counter for signal <cycle_cnt>.
Found 32-bit register for signal <DAT_I_r>.
Found 21-bit comparator equal for signal <do_page_read$cmp_eq0000> created at line 83.
Found 32-bit register for signal <Mtridata_async_d> created at line 310.
@@ -1614,7 +1622,7 @@ WARNING:Xst:646 - Signal <ADDR_I_r> is assigned but never used. This unconnected
Found 1-bit register for signal <async_be<0>>.
Found 1-bit register for signal <async_cs>.
Found 1-bit register for signal <async_rd>.
Found 4-bit down counter for signal <cycle_cnt>.
Found 5-bit down counter for signal <cycle_cnt>.
Found 16-bit register for signal <DAT_I_r>.
Found 16-bit register for signal <Mtridata_async_d> created at line 310.
Found 1-bit register for signal <Mtrien_async_d> created at line 310.
@@ -2852,9 +2860,9 @@ Macro Statistics
3-bit down counter : 4
3-bit updown counter : 1
32-bit up counter : 6
4-bit down counter : 3
4-bit down counter : 1
4-bit up counter : 4
5-bit down counter : 1
5-bit down counter : 3
5-bit up counter : 5
6-bit updown counter : 1
7-bit down counter : 2
@@ -3135,8 +3143,8 @@ Optimizing FSM <inst_flash_port/s/FSM> on signal <s[1:3]> with sequential encodi
idle | 010
leadin | 011
pulse | 100
leadout | 101
release | 110
leadout | unreached
release | 101
---------------------
Analyzing FSM <FSM_10> for best encoding.
Optimizing FSM <inst_ps2_phy_0/Inst_debounce_clk/debounce_cs> on signal <debounce_cs[1:2]> with gray encoding.
@@ -3905,9 +3913,9 @@ Macro Statistics
3-bit down counter : 4
3-bit updown counter : 1
32-bit up counter : 6
4-bit down counter : 3
4-bit down counter : 1
4-bit up counter : 4
5-bit down counter : 1
5-bit down counter : 3
5-bit up counter : 5
6-bit updown counter : 1
7-bit down counter : 2
@@ -4607,6 +4615,7 @@ FlipFlop arb_gnt_1 has been replicated 1 time(s)
FlipFlop inst_clockgen/sys_rst_out has been replicated 11 time(s)
FlipFlop inst_vga_frontend/s_FSM_FFd2 has been replicated 1 time(s)
FlipFlop inst_vga_frontend/s_FSM_FFd5 has been replicated 1 time(s)
FlipFlop inst_vga_frontend/s_FSM_Out51_FRB has been replicated 1 time(s)
Final Macro Processing ...
@@ -4718,8 +4727,8 @@ Unit <mips_sys> processed.
Final Register Report
Macro Statistics
# Registers : 3545
Flip-Flops : 3545
# Registers : 3548
Flip-Flops : 3548
# Shift Registers : 101
2-bit shift register : 3
20-bit shift register : 3
@@ -4754,41 +4763,41 @@ Design Statistics
# IOs : 226
Cell Usage :
# BELS : 6441
# BELS : 6434
# GND : 1
# INV : 95
# LUT1 : 352
# LUT2 : 532
# LUT2_D : 2
# LUT2_L : 2
# LUT3 : 1039
# LUT2 : 537
# LUT2_D : 3
# LUT2_L : 3
# LUT3 : 1062
# LUT3_D : 14
# LUT3_L : 6
# LUT4 : 2181
# LUT4_D : 32
# LUT3_L : 7
# LUT4 : 2160
# LUT4_D : 33
# LUT4_L : 48
# MULT_AND : 6
# MUXCY : 1017
# MUXF5 : 278
# MUXF5 : 260
# MUXF6 : 2
# VCC : 1
# XORCY : 833
# FlipFlops/Latches : 3786
# FD : 314
# FlipFlops/Latches : 3789
# FD : 312
# FD_1 : 85
# FDC : 268
# FDC_1 : 20
# FDCE : 255
# FDCPE : 4
# FDE : 1370
# FDE : 1372
# FDP : 78
# FDPE : 18
# FDR : 191
# FDR : 192
# FDR_1 : 1
# FDRE : 936
# FDRS : 58
# FDRSE : 6
# FDS : 24
# FDS : 26
# FDSE : 84
# IDDR : 32
# ODDR : 42
@@ -4819,10 +4828,10 @@ Device utilization summary:
Selected Device : 4vsx35ff668-10
Number of Slices: 2803 out of 15360 18%
Number of Slice Flip Flops: 3501 out of 30720 11%
Number of 4 input LUTs: 4685 out of 30720 15%
Number used as logic: 4303
Number of Slices: 2790 out of 15360 18%
Number of Slice Flip Flops: 3504 out of 30720 11%
Number of 4 input LUTs: 4696 out of 30720 15%
Number used as logic: 4314
Number used as Shift registers: 176
Number used as RAMs: 206
Number of IOs: 226
@@ -4854,7 +4863,7 @@ Clock Information:
-----------------------------------+---------------------------------------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+---------------------------------------------------------------------------+-------+
sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX | 3379 |
sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX | 3382 |
sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX+inst_clockgen/inst_DCM_SDRCLK_0:CLK270| 68 |
inst_rom_wb/inst_rom/bs_clk0 | BUFG | 98 |
sys_clk_in | inst_clockgen/inst_DCM_VGA_FX:CLKFX | 252 |
@@ -4865,37 +4874,37 @@ inst_rom_wb/inst_rom/bs_update0 | BUFG
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+
RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd2)| 289 |
inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_regi_422) | 96 |
RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/pR_1) | 75 |
inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_18) | 52 |
inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/diff_6) | 29 |
inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_0) | 21 |
inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift19) | 20 |
inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift13) | 20 |
rst_in(rst_in1:O) | NONE(rst_in_shift12) | 20 |
inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/sys_rst_out_4) | 17 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
-----------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+
RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_1) | 290 |
inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_22) | 96 |
RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_1)| 74 |
inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_7) | 52 |
inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pW_3) | 29 |
inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_1) | 21 |
inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift10) | 20 |
inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift8) | 20 |
rst_in(rst_in1:O) | NONE(rst_in_shift1) | 20 |
inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_0) | 17 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+
Timing Summary:
---------------
Speed Grade: -10
Minimum period: 10.566ns (Maximum Frequency: 94.648MHz)
Minimum input arrival time before clock: 8.065ns
Maximum output required time after clock: 10.235ns
Maximum combinational path delay: 9.843ns
Minimum input arrival time before clock: 8.069ns
Maximum output required time after clock: 10.889ns
Maximum combinational path delay: 10.497ns
Timing Detail:
--------------
@@ -4904,7 +4913,7 @@ All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'sys_clk_in'
Clock period: 10.566ns (frequency: 94.648MHz)
Total number of paths / destination ports: 297831 / 8689
Total number of paths / destination ports: 299031 / 8697
-------------------------------------------------------------------------
Delay: 5.283ns (Levels of Logic = 10)
Source: inst_clockgen/sys_rst_out_1 (FF)
@@ -4955,36 +4964,36 @@ Delay: 2.225ns (Levels of Logic = 0)
=========================================================================
Timing constraint: Default period analysis for Clock 'sys_ac97_bit_clk'
Clock period: 5.921ns (frequency: 168.893MHz)
Total number of paths / destination ports: 3602 / 516
Clock period: 5.858ns (frequency: 170.696MHz)
Total number of paths / destination ports: 3598 / 516
-------------------------------------------------------------------------
Delay: 5.921ns (Levels of Logic = 6)
Source: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2 (FF)
Delay: 5.858ns (Levels of Logic = 6)
Source: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (FF)
Destination: inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11 (FF)
Source Clock: sys_ac97_bit_clk rising
Destination Clock: sys_ac97_bit_clk rising
Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2 to inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11
Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 to inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 57 0.360 1.354 inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2 (inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2)
FDRE:C->Q 41 0.360 1.291 inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0)
LUT3:I0->O 25 0.195 1.228 inst_ac97_wb/inst_ac_io/inst_ac_out/varindex0000_cmp_eq000211 (inst_ac97_wb/inst_ac_io/inst_ac_out/N27)
LUT4:I1->O 1 0.195 0.741 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>26 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>26)
LUT4:I0->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105_G (N1345)
LUT4:I0->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105_G (N1312)
MUXF5:I1->O 1 0.374 0.688 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105)
LUT4:I1->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>1691 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>169)
MUXF5:I1->O 1 0.374 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>169_f5 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>)
FDCE:D 0.022 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_9
----------------------------------------
Total 5.921ns (1.910ns logic, 4.011ns route)
(32.3% logic, 67.7% route)
Total 5.858ns (1.910ns logic, 3.948ns route)
(32.6% logic, 67.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_clk_in'
Total number of paths / destination ports: 43744 / 2286
Total number of paths / destination ports: 44076 / 2325
-------------------------------------------------------------------------
Offset: 8.065ns (Levels of Logic = 8)
Offset: 8.069ns (Levels of Logic = 8)
Source: inst_mips_top:ADDR_O<29> (PAD)
Destination: inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 (FF)
Destination Clock: sys_clk_in rising
@@ -4995,16 +5004,16 @@ Offset: 8.065ns (Levels of Logic = 8)
---------------------------------------- ------------
mips_top:ADDR_O<29> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<29>)
LUT4_D:I0->O 3 0.195 0.756 Mmux_ADDR_O221 (ADDR_O<29>)
LUT4_D:I0->LO 1 0.195 0.225 CYC_I_flash_SW0 (N1530)
LUT4:I2->O 39 0.195 1.283 CYC_I_flash (CYC_I_flash)
LUT4_D:I0->LO 1 0.195 0.225 CYC_I_flash_SW0 (N1490)
LUT4:I2->O 40 0.195 1.287 CYC_I_flash (CYC_I_flash)
LUT4:I1->O 1 0.195 0.523 SRDY_I26 (SRDY_I26)
LUT4_D:I3->LO 1 0.195 0.163 SRDY_I36 (N1542)
LUT4_D:I3->LO 1 0.195 0.163 SRDY_I36 (N1500)
LUT3:I2->O 5 0.195 0.546 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/read1 (inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/read)
LUT4_D:I3->O 1 0.195 0.523 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 (N392)
LUT4_D:I3->O 1 0.195 0.523 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 (N391)
LUT3:I2->O 103 0.195 1.205 inst_vga_frontend/inst_bus_fifo/mem_rd_en1 (inst_vga_frontend/inst_bus_fifo/mem_rd_en)
FDE:CE 0.540 inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2
----------------------------------------
Total 8.065ns (2.100ns logic, 5.965ns route)
Total 8.069ns (2.100ns logic, 5.969ns route)
(26.0% logic, 74.0% route)
=========================================================================
@@ -5058,7 +5067,7 @@ Offset: 6.702ns (Levels of Logic = 1)
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IOBUF:IO->O 1 0.965 0.360 sys_sdr_data_31_IOBUF (N398)
IOBUF:IO->O 1 0.965 0.360 sys_sdr_data_31_IOBUF (N397)
IDDR:D 5.377 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data
----------------------------------------
Total 6.702ns (6.342ns logic, 0.360ns route)
@@ -5085,9 +5094,9 @@ Offset: 1.341ns (Levels of Logic = 0)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_clk_in'
Total number of paths / destination ports: 20341 / 226
Total number of paths / destination ports: 19933 / 226
-------------------------------------------------------------------------
Offset: 10.235ns (Levels of Logic = 12)
Offset: 10.889ns (Levels of Logic = 12)
Source: inst_vga_frontend/s_FSM_FFd2_1 (FF)
Destination: inst_mips_top:DAT_I<13> (PAD)
Source Clock: sys_clk_in rising
@@ -5098,21 +5107,21 @@ Offset: 10.235ns (Levels of Logic = 12)
---------------------------------------- ------------
FDRS:C->Q 1 0.360 0.585 inst_vga_frontend/s_FSM_FFd2_1 (inst_vga_frontend/s_FSM_FFd2_1)
LUT2:I0->O 1 0.195 0.523 inst_vga_frontend/s_FSM_Out61 (inst_vga_frontend/CYC_O_blit_src)
LUT4_D:I3->LO 1 0.195 0.163 inst_vga_frontend/CYC_O1 (N1535)
LUT4_D:I3->LO 1 0.195 0.163 inst_vga_frontend/CYC_O1 (N1493)
LUT4:I3->O 8 0.195 0.608 CYC_O1 (CYC_O)
LUT4_D:I3->O 17 0.195 0.961 CYC_I_ac971 (N55)
LUT4_D:I3->O 17 0.195 0.961 CYC_I_ac971 (N57)
LUT4_D:I0->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97)
LUT4:I0->O 1 0.195 0.523 MDAT_I<13>36_SW0 (N1190)
LUT4:I3->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36)
LUT4:I2->O 1 0.195 0.523 MDAT_I<13>84_SW0 (N886)
LUT4:I3->O 1 0.195 0.523 MDAT_I<13>84_SW1 (N1307)
LUT4:I3->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84)
LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N858)
LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1155)
LUT4:I0->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36)
LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N887)
LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1274)
LUT4:I0->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84)
LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N859)
LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>)
mips_top:DAT_I<13> 0.000 inst_mips_top
----------------------------------------
Total 10.235ns (2.700ns logic, 7.535ns route)
(26.4% logic, 73.6% route)
Total 10.889ns (2.700ns logic, 8.189ns route)
(24.8% logic, 75.2% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_ac97_bit_clk'
@@ -5154,9 +5163,9 @@ Offset: 0.720ns (Levels of Logic = 0)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 5508 / 38
Total number of paths / destination ports: 5396 / 38
-------------------------------------------------------------------------
Delay: 9.843ns (Levels of Logic = 11)
Delay: 10.497ns (Levels of Logic = 11)
Source: inst_mips_top:ADDR_O<28> (PAD)
Destination: inst_mips_top:DAT_I<13> (PAD)
@@ -5166,32 +5175,32 @@ Delay: 9.843ns (Levels of Logic = 11)
---------------------------------------- ------------
mips_top:ADDR_O<28> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<28>)
LUT4_D:I0->O 4 0.195 0.702 Mmux_ADDR_O211 (ADDR_O<28>)
LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N390)
LUT4_D:I2->O 17 0.195 0.961 CYC_I_ac971 (N55)
LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N389)
LUT4_D:I2->O 17 0.195 0.961 CYC_I_ac971 (N57)
LUT4_D:I0->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97)
LUT4:I0->O 1 0.195 0.523 MDAT_I<13>36_SW0 (N1190)
LUT4:I3->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36)
LUT4:I2->O 1 0.195 0.523 MDAT_I<13>84_SW0 (N886)
LUT4:I3->O 1 0.195 0.523 MDAT_I<13>84_SW1 (N1307)
LUT4:I3->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84)
LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N858)
LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1155)
LUT4:I0->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36)
LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N887)
LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1274)
LUT4:I0->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84)
LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N859)
LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>)
mips_top:DAT_I<13> 0.000 inst_mips_top
----------------------------------------
Total 9.843ns (2.145ns logic, 7.698ns route)
(21.8% logic, 78.2% route)
Total 10.497ns (2.145ns logic, 8.352ns route)
(20.4% logic, 79.6% route)
=========================================================================
Total REAL time to Xst completion: 118.00 secs
Total CPU time to Xst completion: 117.75 secs
Total REAL time to Xst completion: 123.00 secs
Total CPU time to Xst completion: 122.59 secs
-->
Total memory usage is 338676 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 993 ( 0 filtered)
Number of infos : 143 ( 0 filtered)
Number of warnings : 998 ( 0 filtered)
Number of infos : 144 ( 0 filtered)