From 819028cd9bdbb41d4bf7d220f23c54c27f7bd5c3 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 9 Feb 2010 12:10:10 +0000 Subject: [PATCH] update Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@747 cc03376c-175c-47c8-b038-4cd826a8556b --- .../mips_sys/ise101/mips_sys/mips_sys.par | 137 +- .../mips_sys/ise101/mips_sys/mips_sys.syr | 329 +-- .../mips_sys/ise101/mips_sys/mips_sys.twr | 1767 ++++++++--------- .../mips_sys/ise101/mips_sys/mips_sys_map.mrp | 186 +- 4 files changed, 1122 insertions(+), 1297 deletions(-) diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.par b/projects/mips_sys/ise101/mips_sys/mips_sys.par index 0037ff0..4ea9ab9 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.par +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.par @@ -1,7 +1,7 @@ Release 10.1.03 par K.39 (nt) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -JUPITER:: Sun Feb 07 20:58:29 2010 +JUPITER:: Tue Feb 09 12:58:54 2010 par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd mips_sys.pcf @@ -31,8 +31,8 @@ Device Utilization Summary: Number of OLOGICs 182 out of 448 40% Number of RAMB16s 51 out of 192 26% - Number of Slices 5888 out of 15360 38% - Number of SLICEMs 561 out of 7680 7% + Number of Slices 6053 out of 15360 39% + Number of SLICEMs 549 out of 7680 7% @@ -44,46 +44,54 @@ Finished initial Timing Analysis. REAL time: 14 secs Starting Router -Phase 1: 47772 unrouted; REAL time: 15 secs +Phase 1: 48053 unrouted; REAL time: 16 secs -Phase 2: 40729 unrouted; REAL time: 16 secs +Phase 2: 40978 unrouted; REAL time: 16 secs -Phase 3: 15700 unrouted; REAL time: 22 secs +Phase 3: 15724 unrouted; REAL time: 24 secs -Phase 4: 15700 unrouted; (296275) REAL time: 23 secs +Phase 4: 15724 unrouted; (426198) REAL time: 24 secs -Phase 5: 16428 unrouted; (12142) REAL time: 29 secs +Phase 5: 16453 unrouted; (4039) REAL time: 27 secs -Phase 6: 16484 unrouted; (815) REAL time: 29 secs +Phase 6: 16476 unrouted; (459) REAL time: 27 secs -Phase 7: 0 unrouted; (10463) REAL time: 1 mins +Phase 7: 0 unrouted; (12926) REAL time: 55 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 8: 0 unrouted; (10463) REAL time: 2 mins 43 secs +Phase 8: 0 unrouted; (7751) REAL time: 1 mins 38 secs -Phase 9: 0 unrouted; (6271) REAL time: 2 mins 55 secs +Phase 9: 0 unrouted; (4297) REAL time: 2 mins 14 secs -Phase 10: 0 unrouted; (6221) REAL time: 3 mins 2 secs - -Phase 11: 0 unrouted; (6221) REAL time: 3 mins 3 secs +Phase 10: 0 unrouted; (4297) REAL time: 3 mins 13 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 12: 0 unrouted; (5742) REAL time: 4 mins 18 secs +Phase 11: 0 unrouted; (3077) REAL time: 3 mins 31 secs -Phase 13: 0 unrouted; (5742) REAL time: 4 mins 32 secs +Phase 12: 0 unrouted; (1330) REAL time: 3 mins 38 secs + +Phase 13: 0 unrouted; (1330) REAL time: 3 mins 39 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 14: 0 unrouted; (483) REAL time: 4 mins 57 secs +Phase 14: 0 unrouted; (1207) REAL time: 5 mins 31 secs -Phase 15: 0 unrouted; (483) REAL time: 5 mins 1 secs +Updating file: mips_sys.ncd with current fully routed design. -Phase 16: 0 unrouted; (483) REAL time: 5 mins 6 secs +Phase 15: 0 unrouted; (0) REAL time: 8 mins 27 secs -Total REAL time to Router completion: 5 mins 8 secs -Total CPU time to Router completion: 4 mins 55 secs +Phase 16: 0 unrouted; (0) REAL time: 8 mins 28 secs + +Updating file: mips_sys.ncd with current fully routed design. + +Phase 17: 0 unrouted; (0) REAL time: 8 mins 47 secs + +Phase 18: 0 unrouted; (0) REAL time: 8 mins 53 secs + +Total REAL time to Router completion: 8 mins 55 secs +Total CPU time to Router completion: 8 mins 32 secs Partition Implementation Status ------------------------------- @@ -101,28 +109,28 @@ Generating Clock Report +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ -| cpu_clk |BUFGCTRL_X0Y12| No | 1616 | 0.434 | 4.046 | -+---------------------+--------------+------+------+------------+-------------+ -| CLK_O | BUFGCTRL_X0Y2| No | 2299 | 0.544 | 3.933 | -+---------------------+--------------+------+------+------------+-------------+ -| vga_clk |BUFGCTRL_X0Y11| No | 170 | 0.400 | 3.881 | -+---------------------+--------------+------+------+------------+-------------+ -| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 67 | 0.241 | 3.697 | -+---------------------+--------------+------+------+------------+-------------+ -| sdram_clk0 |BUFGCTRL_X0Y31| No | 237 | 0.383 | 3.933 | -+---------------------+--------------+------+------+------------+-------------+ |inst_rom_wb/inst_rom | | | | | | -| /bs_clk1 | BUFGCTRL_X0Y0| No | 71 | 0.159 | 3.562 | +| /bs_clk1 | BUFGCTRL_X0Y0| No | 72 | 0.251 | 3.733 | ++---------------------+--------------+------+------+------------+-------------+ +| CLK_O | BUFGCTRL_X0Y2| No | 2351 | 0.515 | 3.904 | ++---------------------+--------------+------+------+------------+-------------+ +| cpu_clk |BUFGCTRL_X0Y12| No | 1601 | 0.402 | 4.005 | ++---------------------+--------------+------+------+------------+-------------+ +| vga_clk |BUFGCTRL_X0Y11| No | 175 | 0.394 | 3.881 | +---------------------+--------------+------+------+------------+-------------+ |sys_ac97_bit_clk_IBU | | | | | | -| F | BUFGCTRL_X0Y8| No | 253 | 0.397 | 3.865 | +| F | BUFGCTRL_X0Y8| No | 262 | 0.414 | 3.851 | +---------------------+--------------+------+------+------------+-------------+ -| sdram_clk270 |BUFGCTRL_X0Y16| No | 66 | 0.173 | 3.932 | +| sdram_clk0 |BUFGCTRL_X0Y31| No | 233 | 0.527 | 3.933 | ++---------------------+--------------+------+------+------------+-------------+ +| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 59 | 0.346 | 3.799 | ++---------------------+--------------+------+------+------------+-------------+ +| sdram_clk270 |BUFGCTRL_X0Y16| No | 67 | 0.174 | 3.932 | +---------------------+--------------+------+------+------------+-------------+ | sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 | +---------------------+--------------+------+------+------------+-------------+ |inst_rom_wb/inst_rom | | | | | | -| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.035 | 3.487 | +| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.018 | 3.605 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing @@ -130,20 +138,7 @@ only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. -Timing Score: 483 - -WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in - your design. - - Review the timing report using Timing Analyzer (In ISE select "Post-Place & - Route Static Timing Report"). Go to the failing constraint(s) and select - the "Timing Improvement Wizard" link for suggestions to correct each problem. - - Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to - ensure the best options are set in the tools for timing closure. - - Use the Xilinx "SmartXplorer" script to try special combinations of - options known to produce very good results. +Timing Score: 0 INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. @@ -154,33 +149,31 @@ Asterisk (*) preceding a constraint indicates it was not met. Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ -* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.118ns| 10.018ns| 5| 483 - ns HIGH 50% | HOLD | 0.383ns| | 0| 0 + TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | 0.001ns| 9.899ns| 0| 0 + ns HIGH 50% | HOLD | 0.309ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.010ns| 7.990ns| 0| 0 - s HIGH 50% | HOLD | 0.508ns| | 0| 0 + TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | 0.020ns| 9.880ns| 0| 0 + HIGH 50% | HOLD | 0.359ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.072ns| 7.356ns| 0| 0 - 7.5 ns HIGH 50% | HOLD | 0.515ns| | 0| 0 + TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.077ns| 7.923ns| 0| 0 + s HIGH 50% | HOLD | 0.490ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | 0.164ns| 9.736ns| 0| 0 - HIGH 50% | HOLD | 0.326ns| | 0| 0 + TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.152ns| 7.348ns| 0| 0 + 7.5 ns HIGH 50% | HOLD | 0.511ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 36.549ns| 6.902ns| 0| 0 - ns HIGH 50% | HOLD | 0.480ns| | 0| 0 + NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 35.794ns| 9.594ns| 0| 0 + ns HIGH 50% | HOLD | 0.509ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 74.795ns| 5.205ns| 0| 0 - ns HIGH 50% | HOLD | 0.824ns| | 0| 0 + TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 73.898ns| 6.102ns| 0| 0 + ns HIGH 50% | HOLD | 0.852ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.446ns| N/A| 0 + PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.779ns| N/A| 0 ------------------------------------------------------------------------------------------------------ - PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.486ns| N/A| 0 ------------------------------------------------------------------------------------------------------- - PATH "TS_unrelate_CPU_path" TIG | MAXDELAY| N/A| 8.192ns| N/A| 0 + PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.002ns| N/A| 0 ------------------------------------------------------------------------------------------------------ -1 constraint not met. +All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. @@ -189,17 +182,17 @@ Generating Pad Report. All signals are completely routed. -Total REAL time to PAR completion: 5 mins 17 secs -Total CPU time to PAR completion: 5 mins 1 secs +Total REAL time to PAR completion: 9 mins 7 secs +Total CPU time to PAR completion: 8 mins 40 secs -Peak Memory Usage: 418 MB +Peak Memory Usage: 425 MB Placer: Placement generated during map. Routing: Completed - No errors found. -Timing: Completed - 5 errors found. +Timing: Completed - No errors found. Number of error messages: 0 -Number of warning messages: 1 +Number of warning messages: 0 Number of info messages: 1 Writing design to file mips_sys.ncd diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.syr b/projects/mips_sys/ise101/mips_sys/mips_sys.syr index 3763f79..71ac1df 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.syr +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.06 secs +Total CPU time to Xst completion: 0.08 secs --> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.06 secs +Total CPU time to Xst completion: 0.08 secs --> Reading design: mips_sys.prj @@ -128,6 +128,7 @@ Architecture behavioral of Entity fifo_async_ctrl is up to date. Compiling vhdl file "W:/vhdl/lib/misc/dpram_1w1r.vhd" in Library work. Architecture behavioral of Entity dpram_1w1r is up to date. Compiling vhdl file "W:/vhdl/lib/misc/utils_pkg.vhd" in Library work. +WARNING:HDLParsers:3534 - "W:/vhdl/lib/misc/utils_pkg.vhd" Line 155. In the function f_correct, not all control paths contain a return statement. Architecture utils_pkg of Entity utils_pkg is up to date. Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd" in Library work. Architecture behavioral of Entity ac_in is up to date. @@ -156,7 +157,8 @@ Architecture low_level_definition of Entity kcuart_tx is up to date. Compiling vhdl file "W:/vhdl/lib/ps2_port/src/debounce.vhd" in Library work. Architecture behavioral of Entity debounce is up to date. Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" in Library work. -Architecture behavioral of Entity ps2_core is up to date. +Entity compiled. +Entity (Architecture ) compiled. Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync.vhd" in Library work. Architecture behavioral of Entity fifo_sync is up to date. Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd" in Library work. @@ -174,7 +176,8 @@ Architecture macro_level_definition of Entity uart_rx is up to date. Compiling vhdl file "W:/vhdl/lib/misc/async_types.vhd" in Library work. Architecture async_types of Entity async_types is up to date. Compiling vhdl file "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd" in Library work. -Architecture data of Entity rom is up to date. +Entity compiled. +Entity (Architecture ) compiled. Compiling vhdl file "W:/vhdl/lib/CPUs/MIPS/src/core/mips_types.vhd" in Library work. Architecture mips_types of Entity mips_types is up to date. Compiling vhdl file "W:/vhdl/projects/mips_sys/src/async_defs.vhd" in Library work. @@ -183,7 +186,8 @@ Architecture behavior of Entity rom_wb is up to date. Compiling vhdl file "W:/vhdl/lib/misc/lcd_port.vhd" in Library work. Architecture behavioral of Entity lcd_port is up to date. Compiling vhdl file "W:/vhdl/lib/misc/gpio_wb.vhd" in Library work. -Architecture behavior of Entity gpio_wb is up to date. +Entity compiled. +Entity (Architecture ) compiled. Compiling vhdl file "W:/vhdl/lib/misc/async_port_wb.vhd" in Library work. Architecture behavioral of Entity async_port_wb is up to date. Compiling vhdl file "W:/vhdl/lib/uart/uart_wb.vhd" in Library work. @@ -201,17 +205,15 @@ Architecture behavior of Entity ps2_wb is up to date. Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd" in Library work. Architecture behavioral of Entity ps2_phy is up to date. Compiling vhdl file "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. +Architecture behavior of Entity mips_sys is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ) with generics. - ddr_frequency_hz = 100000000 - ddr_phaseshift = 0 - sys_freq = 100000000 - sys_freq_in = 100000000 + sdram_phaseshift = 0 + sys_freq = 100.000000 + sys_freq_in = 100.000000 tsvga = (f_pxl_clk => 40000000 nfps => 60 ts_h => (ncyc_scan => 800 @@ -229,7 +231,8 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ). -Analyzing hierarchy for entity in library (architecture ). +Analyzing hierarchy for entity in library (architecture ) with generics. + f_sysclk = 100.000000 Analyzing hierarchy for entity in library (architecture ) with generics. addr_width = 25 @@ -249,7 +252,7 @@ Analyzing hierarchy for entity in library (architecture < pol_rst => '0') byte_sel_width = 1 data_width = 32 - f_sysclk_hz = 100000000 + f_sysclk = 100.000000 Analyzing hierarchy for entity in library (architecture ) with generics. addr_width = 4 @@ -269,21 +272,25 @@ Analyzing hierarchy for entity in library (architecture < pol_rst => '0') byte_sel_width = 1 data_width = 16 - f_sysclk_hz = 100000000 + f_sysclk = 100.000000 Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ) with generics. - clk_in_freq_hz = 100000000 + clk_in_freq = 100.000000 sdr0_clk_out_phaseshift = 0 sdr1_clk_out_phaseshift = 0 - sys_clk_out_freq_hz = 100000000 - vga_clk_out_freq_hz = 40000000 + sys_clk_out_freq = 100.000000 + vga_clk_out_freq = 40.000000 +WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored. +WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored. +WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored. +WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored. Analyzing hierarchy for entity in library (architecture ) with generics. BL = 2 - f_sdrclk_hz = 100000000 - f_sysclk_hz = 100000000 + f_sdrclk = 100.000000 + f_sysclk = 100.000000 fifo_depth = 5 Analyzing hierarchy for entity in library (architecture ) with generics. @@ -307,7 +314,7 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ) with generics. - f_sys_clk_hz = 100000000 + f_sys_clk = 100.000000 Analyzing hierarchy for entity in library (architecture ). @@ -337,8 +344,8 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ) with generics. BL = 2 - f_sdrclk_hz = 100000000 - f_sysclk_hz = 100000000 + f_sdrclk = 100.000000 + f_sysclk = 100.000000 fifo_depth = 5 Analyzing hierarchy for entity in library (architecture ) with generics. @@ -406,7 +413,7 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ). Analyzing hierarchy for entity in library (architecture ) with generics. - f_sys_clk_hz = 100000000 + f_sys_clk = 100.000000 Analyzing hierarchy for entity in library (architecture ) with generics. ncyc_latency = 8 @@ -441,7 +448,7 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ) with generics. BL = 2 - f_sysclk_hz = 100000000 + f_sysclk = 100.000000 Analyzing hierarchy for entity in library (architecture ) with generics. addr_width = 5 @@ -451,7 +458,7 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ) with generics. BL = 2 - f_sdrclk_hz = 100000000 + f_sdrclk = 100.000000 Analyzing hierarchy for entity in library (architecture ). @@ -576,10 +583,9 @@ WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 333: attribute on insta * HDL Analysis * ========================================================================= Analyzing generic Entity in library (Architecture ). - ddr_frequency_hz = 100000000 - ddr_phaseshift = 0 - sys_freq = 100000000 - sys_freq_in = 100000000 + sdram_phaseshift = 0 + sys_freq = 100.000000 + sys_freq_in = 100.000000 tsvga = (f_pxl_clk => 40000000 nfps => 60 ts_h => (ncyc_scan => 800 @@ -597,12 +603,12 @@ Analyzing generic Entity in library (Architecture ). Set user-defined property "KEEP = TRUE" for signal . Set user-defined property "KEEP = TRUE" for signal . Set user-defined property "KEEP = TRUE" for signal . -WARNING:Xst:2211 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 674: Instantiating black box module . -WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 711: Unconnected output port 'dout' of component 'lcd_port'. -WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 748: Unconnected output port 'async_be' of component 'async_port_wb'. -WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 781: Unconnected output port 'async_be' of component 'async_port_wb'. -WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 781: Unconnected output port 'async_rst' of component 'async_port_wb'. -WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 855: Unconnected output port 'sdr1_clk0_out' of component 'clockgen'. +WARNING:Xst:2211 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 678: Instantiating black box module . +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 715: Unconnected output port 'dout' of component 'lcd_port'. +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 756: Unconnected output port 'async_be' of component 'async_port_wb'. +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 789: Unconnected output port 'async_be' of component 'async_port_wb'. +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 789: Unconnected output port 'async_rst' of component 'async_port_wb'. +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 863: Unconnected output port 'sdr1_clk0_out' of component 'clockgen'. Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). @@ -615,7 +621,8 @@ Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. -Analyzing Entity in library (Architecture ). +Analyzing generic Entity in library (Architecture ). + f_sysclk = 100.000000 Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -636,7 +643,7 @@ Analyzing generic Entity in library (Architecture '0') byte_sel_width = 1 data_width = 32 - f_sysclk_hz = 100000000 + f_sysclk = 100.000000 Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -657,7 +664,7 @@ Analyzing generic Entity in library (Architecture '0') byte_sel_width = 1 data_width = 16 - f_sysclk_hz = 100000000 + f_sysclk = 100.000000 Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). @@ -786,11 +793,11 @@ Analyzing Entity in library (Architecture analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). - clk_in_freq_hz = 100000000 + clk_in_freq = 100.000000 sdr0_clk_out_phaseshift = 0 sdr1_clk_out_phaseshift = 0 - sys_clk_out_freq_hz = 100000000 - vga_clk_out_freq_hz = 40000000 + sys_clk_out_freq = 100.000000 + vga_clk_out_freq = 40.000000 Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance in unit . Set user-defined property "CLKFX_DIVIDE = 5" for instance in unit . Set user-defined property "CLKFX_MULTIPLY = 2" for instance in unit . @@ -861,8 +868,8 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). BL = 2 - f_sdrclk_hz = 100000000 - f_sysclk_hz = 100000000 + f_sdrclk = 100.000000 + f_sysclk = 100.000000 fifo_depth = 5 WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_afull' of component 'fifo_sync'. WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_aempty' of component 'fifo_sync'. @@ -927,8 +934,8 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). BL = 2 - f_sdrclk_hz = 100000000 - f_sysclk_hz = 100000000 + f_sdrclk = 100.000000 + f_sysclk = 100.000000 fifo_depth = 5 WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_afull' of component 'fifo_async'. WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_aempty' of component 'fifo_async'. @@ -936,7 +943,7 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). BL = 2 - f_sysclk_hz = 100000000 + f_sysclk = 100.000000 Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -953,7 +960,7 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). BL = 2 - f_sdrclk_hz = 100000000 + f_sdrclk = 100.000000 Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). @@ -1419,7 +1426,7 @@ WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" line 128: Index va Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). - f_sys_clk_hz = 100000000 + f_sys_clk = 100.000000 INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. @@ -1439,7 +1446,7 @@ INFO:Xst:2679 - Register > in unit has a constant value of 0 Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). - f_sys_clk_hz = 100000000 + f_sys_clk = 100.000000 WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 191: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 204: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: @@ -1500,10 +1507,10 @@ WARNING:Xst:1780 - Signal is never used or assigned. This uncon Found 1-bit register for signal . Found 32-bit up counter for signal . Found 1-bit register for signal . - Found 32-bit comparator less for signal created at line 254. + Found 32-bit comparator less for signal created at line 259. Found 1-bit register for signal . Found 32-bit up counter for signal . - Found 32-bit comparator greatequal for signal created at line 254. + Found 32-bit comparator greatequal for signal created at line 259. Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . @@ -1512,20 +1519,20 @@ WARNING:Xst:1780 - Signal is never used or assigned. This uncon Found 32-bit register for signal . Found 32-bit register for signal . Found 7-bit up counter for signal . - Found 7-bit comparator greatequal for signal created at line 236. + Found 7-bit comparator greatequal for signal created at line 241. Found 64-bit register for signal . Found 2-bit register for signal . Found 32-bit up counter for signal . - Found 32-bit comparator greatequal for signal created at line 291. - Found 32-bit comparator greatequal for signal created at line 291. + Found 32-bit comparator greatequal for signal created at line 296. + Found 32-bit comparator greatequal for signal created at line 296. Found 2-bit register for signal . Found 2-bit register for signal . Found 2-bit register for signal . Found 2-bit register for signal . Found 2-bit register for signal . Found 2-bit register for signal . - Found 32-bit comparator less for signal created at line 291. - Found 32-bit comparator less for signal created at line 291. + Found 32-bit comparator less for signal created at line 296. + Found 32-bit comparator less for signal created at line 296. Summary: inferred 5 Counter(s). inferred 339 D-type flip-flop(s). @@ -1541,12 +1548,13 @@ WARNING:Xst:647 - Input is never used. This port will be preserved and WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +INFO:Xst:1799 - State leadout is never reached in FSM . Found finite state machine for signal . ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 15 | - | Inputs | 3 | - | Outputs | 6 | + | States | 6 | + | Transitions | 14 | + | Inputs | 4 | + | Outputs | 5 | | Clock | CLK_I (rising_edge) | | Reset | RST_I (positive) | | Reset type | synchronous | @@ -1565,7 +1573,7 @@ WARNING:Xst:646 - Signal > is assigned but never used. This unconn Found 1-bit register for signal . Found 1-bit register for signal . Found 25-bit register for signal . - Found 4-bit down counter for signal . + Found 5-bit down counter for signal . Found 32-bit register for signal . Found 21-bit comparator equal for signal created at line 83. Found 32-bit register for signal created at line 310. @@ -1614,7 +1622,7 @@ WARNING:Xst:646 - Signal is assigned but never used. This unconnected Found 1-bit register for signal >. Found 1-bit register for signal . Found 1-bit register for signal . - Found 4-bit down counter for signal . + Found 5-bit down counter for signal . Found 16-bit register for signal . Found 16-bit register for signal created at line 310. Found 1-bit register for signal created at line 310. @@ -2852,9 +2860,9 @@ Macro Statistics 3-bit down counter : 4 3-bit updown counter : 1 32-bit up counter : 6 - 4-bit down counter : 3 + 4-bit down counter : 1 4-bit up counter : 4 - 5-bit down counter : 1 + 5-bit down counter : 3 5-bit up counter : 5 6-bit updown counter : 1 7-bit down counter : 2 @@ -3135,8 +3143,8 @@ Optimizing FSM on signal with sequential encodi idle | 010 leadin | 011 pulse | 100 - leadout | 101 - release | 110 + leadout | unreached + release | 101 --------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. @@ -3905,9 +3913,9 @@ Macro Statistics 3-bit down counter : 4 3-bit updown counter : 1 32-bit up counter : 6 - 4-bit down counter : 3 + 4-bit down counter : 1 4-bit up counter : 4 - 5-bit down counter : 1 + 5-bit down counter : 3 5-bit up counter : 5 6-bit updown counter : 1 7-bit down counter : 2 @@ -4607,6 +4615,7 @@ FlipFlop arb_gnt_1 has been replicated 1 time(s) FlipFlop inst_clockgen/sys_rst_out has been replicated 11 time(s) FlipFlop inst_vga_frontend/s_FSM_FFd2 has been replicated 1 time(s) FlipFlop inst_vga_frontend/s_FSM_FFd5 has been replicated 1 time(s) +FlipFlop inst_vga_frontend/s_FSM_Out51_FRB has been replicated 1 time(s) Final Macro Processing ... @@ -4718,8 +4727,8 @@ Unit processed. Final Register Report Macro Statistics -# Registers : 3545 - Flip-Flops : 3545 +# Registers : 3548 + Flip-Flops : 3548 # Shift Registers : 101 2-bit shift register : 3 20-bit shift register : 3 @@ -4754,41 +4763,41 @@ Design Statistics # IOs : 226 Cell Usage : -# BELS : 6441 +# BELS : 6434 # GND : 1 # INV : 95 # LUT1 : 352 -# LUT2 : 532 -# LUT2_D : 2 -# LUT2_L : 2 -# LUT3 : 1039 +# LUT2 : 537 +# LUT2_D : 3 +# LUT2_L : 3 +# LUT3 : 1062 # LUT3_D : 14 -# LUT3_L : 6 -# LUT4 : 2181 -# LUT4_D : 32 +# LUT3_L : 7 +# LUT4 : 2160 +# LUT4_D : 33 # LUT4_L : 48 # MULT_AND : 6 # MUXCY : 1017 -# MUXF5 : 278 +# MUXF5 : 260 # MUXF6 : 2 # VCC : 1 # XORCY : 833 -# FlipFlops/Latches : 3786 -# FD : 314 +# FlipFlops/Latches : 3789 +# FD : 312 # FD_1 : 85 # FDC : 268 # FDC_1 : 20 # FDCE : 255 # FDCPE : 4 -# FDE : 1370 +# FDE : 1372 # FDP : 78 # FDPE : 18 -# FDR : 191 +# FDR : 192 # FDR_1 : 1 # FDRE : 936 # FDRS : 58 # FDRSE : 6 -# FDS : 24 +# FDS : 26 # FDSE : 84 # IDDR : 32 # ODDR : 42 @@ -4819,10 +4828,10 @@ Device utilization summary: Selected Device : 4vsx35ff668-10 - Number of Slices: 2803 out of 15360 18% - Number of Slice Flip Flops: 3501 out of 30720 11% - Number of 4 input LUTs: 4685 out of 30720 15% - Number used as logic: 4303 + Number of Slices: 2790 out of 15360 18% + Number of Slice Flip Flops: 3504 out of 30720 11% + Number of 4 input LUTs: 4696 out of 30720 15% + Number used as logic: 4314 Number used as Shift registers: 176 Number used as RAMs: 206 Number of IOs: 226 @@ -4854,7 +4863,7 @@ Clock Information: -----------------------------------+---------------------------------------------------------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+---------------------------------------------------------------------------+-------+ -sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX | 3379 | +sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX | 3382 | sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX+inst_clockgen/inst_DCM_SDRCLK_0:CLK270| 68 | inst_rom_wb/inst_rom/bs_clk0 | BUFG | 98 | sys_clk_in | inst_clockgen/inst_DCM_VGA_FX:CLKFX | 252 | @@ -4865,37 +4874,37 @@ inst_rom_wb/inst_rom/bs_update0 | BUFG Asynchronous Control Signals Information: ---------------------------------------- ------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | ------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+ -RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd2)| 289 | -inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_regi_422) | 96 | -RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/pR_1) | 75 | -inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_18) | 52 | -inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/diff_6) | 29 | -inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_0) | 21 | -inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift19) | 20 | -inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift13) | 20 | -rst_in(rst_in1:O) | NONE(rst_in_shift12) | 20 | -inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/sys_rst_out_4) | 17 | -inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | ------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+ +-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+ +RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_1) | 290 | +inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_22) | 96 | +RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_1)| 74 | +inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_7) | 52 | +inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pW_3) | 29 | +inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_1) | 21 | +inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift10) | 20 | +inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift8) | 20 | +rst_in(rst_in1:O) | NONE(rst_in_shift1) | 20 | +inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_0) | 17 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+ Timing Summary: --------------- Speed Grade: -10 Minimum period: 10.566ns (Maximum Frequency: 94.648MHz) - Minimum input arrival time before clock: 8.065ns - Maximum output required time after clock: 10.235ns - Maximum combinational path delay: 9.843ns + Minimum input arrival time before clock: 8.069ns + Maximum output required time after clock: 10.889ns + Maximum combinational path delay: 10.497ns Timing Detail: -------------- @@ -4904,7 +4913,7 @@ All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'sys_clk_in' Clock period: 10.566ns (frequency: 94.648MHz) - Total number of paths / destination ports: 297831 / 8689 + Total number of paths / destination ports: 299031 / 8697 ------------------------------------------------------------------------- Delay: 5.283ns (Levels of Logic = 10) Source: inst_clockgen/sys_rst_out_1 (FF) @@ -4955,36 +4964,36 @@ Delay: 2.225ns (Levels of Logic = 0) ========================================================================= Timing constraint: Default period analysis for Clock 'sys_ac97_bit_clk' - Clock period: 5.921ns (frequency: 168.893MHz) - Total number of paths / destination ports: 3602 / 516 + Clock period: 5.858ns (frequency: 170.696MHz) + Total number of paths / destination ports: 3598 / 516 ------------------------------------------------------------------------- -Delay: 5.921ns (Levels of Logic = 6) - Source: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2 (FF) +Delay: 5.858ns (Levels of Logic = 6) + Source: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (FF) Destination: inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11 (FF) Source Clock: sys_ac97_bit_clk rising Destination Clock: sys_ac97_bit_clk rising - Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2 to inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11 + Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 to inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDRE:C->Q 57 0.360 1.354 inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2 (inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2) + FDRE:C->Q 41 0.360 1.291 inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0) LUT3:I0->O 25 0.195 1.228 inst_ac97_wb/inst_ac_io/inst_ac_out/varindex0000_cmp_eq000211 (inst_ac97_wb/inst_ac_io/inst_ac_out/N27) LUT4:I1->O 1 0.195 0.741 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>26 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>26) - LUT4:I0->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105_G (N1345) + LUT4:I0->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105_G (N1312) MUXF5:I1->O 1 0.374 0.688 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105) LUT4:I1->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>1691 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>169) MUXF5:I1->O 1 0.374 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>169_f5 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>) FDCE:D 0.022 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_9 ---------------------------------------- - Total 5.921ns (1.910ns logic, 4.011ns route) - (32.3% logic, 67.7% route) + Total 5.858ns (1.910ns logic, 3.948ns route) + (32.6% logic, 67.4% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_clk_in' - Total number of paths / destination ports: 43744 / 2286 + Total number of paths / destination ports: 44076 / 2325 ------------------------------------------------------------------------- -Offset: 8.065ns (Levels of Logic = 8) +Offset: 8.069ns (Levels of Logic = 8) Source: inst_mips_top:ADDR_O<29> (PAD) Destination: inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 (FF) Destination Clock: sys_clk_in rising @@ -4995,16 +5004,16 @@ Offset: 8.065ns (Levels of Logic = 8) ---------------------------------------- ------------ mips_top:ADDR_O<29> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<29>) LUT4_D:I0->O 3 0.195 0.756 Mmux_ADDR_O221 (ADDR_O<29>) - LUT4_D:I0->LO 1 0.195 0.225 CYC_I_flash_SW0 (N1530) - LUT4:I2->O 39 0.195 1.283 CYC_I_flash (CYC_I_flash) + LUT4_D:I0->LO 1 0.195 0.225 CYC_I_flash_SW0 (N1490) + LUT4:I2->O 40 0.195 1.287 CYC_I_flash (CYC_I_flash) LUT4:I1->O 1 0.195 0.523 SRDY_I26 (SRDY_I26) - LUT4_D:I3->LO 1 0.195 0.163 SRDY_I36 (N1542) + LUT4_D:I3->LO 1 0.195 0.163 SRDY_I36 (N1500) LUT3:I2->O 5 0.195 0.546 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/read1 (inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/read) - LUT4_D:I3->O 1 0.195 0.523 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 (N392) + LUT4_D:I3->O 1 0.195 0.523 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 (N391) LUT3:I2->O 103 0.195 1.205 inst_vga_frontend/inst_bus_fifo/mem_rd_en1 (inst_vga_frontend/inst_bus_fifo/mem_rd_en) FDE:CE 0.540 inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 ---------------------------------------- - Total 8.065ns (2.100ns logic, 5.965ns route) + Total 8.069ns (2.100ns logic, 5.969ns route) (26.0% logic, 74.0% route) ========================================================================= @@ -5058,7 +5067,7 @@ Offset: 6.702ns (Levels of Logic = 1) Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IOBUF:IO->O 1 0.965 0.360 sys_sdr_data_31_IOBUF (N398) + IOBUF:IO->O 1 0.965 0.360 sys_sdr_data_31_IOBUF (N397) IDDR:D 5.377 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data ---------------------------------------- Total 6.702ns (6.342ns logic, 0.360ns route) @@ -5085,9 +5094,9 @@ Offset: 1.341ns (Levels of Logic = 0) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_clk_in' - Total number of paths / destination ports: 20341 / 226 + Total number of paths / destination ports: 19933 / 226 ------------------------------------------------------------------------- -Offset: 10.235ns (Levels of Logic = 12) +Offset: 10.889ns (Levels of Logic = 12) Source: inst_vga_frontend/s_FSM_FFd2_1 (FF) Destination: inst_mips_top:DAT_I<13> (PAD) Source Clock: sys_clk_in rising @@ -5098,21 +5107,21 @@ Offset: 10.235ns (Levels of Logic = 12) ---------------------------------------- ------------ FDRS:C->Q 1 0.360 0.585 inst_vga_frontend/s_FSM_FFd2_1 (inst_vga_frontend/s_FSM_FFd2_1) LUT2:I0->O 1 0.195 0.523 inst_vga_frontend/s_FSM_Out61 (inst_vga_frontend/CYC_O_blit_src) - LUT4_D:I3->LO 1 0.195 0.163 inst_vga_frontend/CYC_O1 (N1535) + LUT4_D:I3->LO 1 0.195 0.163 inst_vga_frontend/CYC_O1 (N1493) LUT4:I3->O 8 0.195 0.608 CYC_O1 (CYC_O) - LUT4_D:I3->O 17 0.195 0.961 CYC_I_ac971 (N55) + LUT4_D:I3->O 17 0.195 0.961 CYC_I_ac971 (N57) LUT4_D:I0->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97) - LUT4:I0->O 1 0.195 0.523 MDAT_I<13>36_SW0 (N1190) - LUT4:I3->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36) - LUT4:I2->O 1 0.195 0.523 MDAT_I<13>84_SW0 (N886) - LUT4:I3->O 1 0.195 0.523 MDAT_I<13>84_SW1 (N1307) - LUT4:I3->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84) - LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N858) + LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1155) + LUT4:I0->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36) + LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N887) + LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1274) + LUT4:I0->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84) + LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N859) LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>) mips_top:DAT_I<13> 0.000 inst_mips_top ---------------------------------------- - Total 10.235ns (2.700ns logic, 7.535ns route) - (26.4% logic, 73.6% route) + Total 10.889ns (2.700ns logic, 8.189ns route) + (24.8% logic, 75.2% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_ac97_bit_clk' @@ -5154,9 +5163,9 @@ Offset: 0.720ns (Levels of Logic = 0) ========================================================================= Timing constraint: Default path analysis - Total number of paths / destination ports: 5508 / 38 + Total number of paths / destination ports: 5396 / 38 ------------------------------------------------------------------------- -Delay: 9.843ns (Levels of Logic = 11) +Delay: 10.497ns (Levels of Logic = 11) Source: inst_mips_top:ADDR_O<28> (PAD) Destination: inst_mips_top:DAT_I<13> (PAD) @@ -5166,32 +5175,32 @@ Delay: 9.843ns (Levels of Logic = 11) ---------------------------------------- ------------ mips_top:ADDR_O<28> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<28>) LUT4_D:I0->O 4 0.195 0.702 Mmux_ADDR_O211 (ADDR_O<28>) - LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N390) - LUT4_D:I2->O 17 0.195 0.961 CYC_I_ac971 (N55) + LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N389) + LUT4_D:I2->O 17 0.195 0.961 CYC_I_ac971 (N57) LUT4_D:I0->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97) - LUT4:I0->O 1 0.195 0.523 MDAT_I<13>36_SW0 (N1190) - LUT4:I3->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36) - LUT4:I2->O 1 0.195 0.523 MDAT_I<13>84_SW0 (N886) - LUT4:I3->O 1 0.195 0.523 MDAT_I<13>84_SW1 (N1307) - LUT4:I3->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84) - LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N858) + LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1155) + LUT4:I0->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36) + LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N887) + LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1274) + LUT4:I0->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84) + LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N859) LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>) mips_top:DAT_I<13> 0.000 inst_mips_top ---------------------------------------- - Total 9.843ns (2.145ns logic, 7.698ns route) - (21.8% logic, 78.2% route) + Total 10.497ns (2.145ns logic, 8.352ns route) + (20.4% logic, 79.6% route) ========================================================================= -Total REAL time to Xst completion: 118.00 secs -Total CPU time to Xst completion: 117.75 secs +Total REAL time to Xst completion: 123.00 secs +Total CPU time to Xst completion: 122.59 secs --> Total memory usage is 338676 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 993 ( 0 filtered) -Number of infos : 143 ( 0 filtered) +Number of warnings : 998 ( 0 filtered) +Number of infos : 144 ( 0 filtered) diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.twr b/projects/mips_sys/ise101/mips_sys/mips_sys.twr index 5b2af52..5f3c4a2 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.twr +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.twr @@ -28,64 +28,16 @@ INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on ================================================================================ Timing constraint: NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 ns HIGH 50%; - 3542 paths analyzed, 641 endpoints analyzed, 0 failing endpoints + 3548 paths analyzed, 640 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 6.902ns. + Minimum period is 9.594ns. -------------------------------------------------------------------------------- -Slack: 36.549ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF) - Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 (FF) - Requirement: 40.000ns - Data Path Delay: 3.451ns (Levels of Logic = 0) - Clock Path Skew: 0.000ns - Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns - Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns - Clock Uncertainty: 0.000ns - - Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X61Y38.YQ Tcko 0.286 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> - inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 - SLICE_X29Y62.BY net (fanout=14) 2.873 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> - SLICE_X29Y62.CLK Tdick 0.292 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 - inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 - ------------------------------------------------- --------------------------- - Total 3.451ns (0.578ns logic, 2.873ns route) - (16.7% logic, 83.3% route) - --------------------------------------------------------------------------------- -Slack: 36.837ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 (FF) - Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 (FF) - Requirement: 40.000ns - Data Path Delay: 3.124ns (Levels of Logic = 0) - Clock Path Skew: -0.039ns (2.691 - 2.730) - Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns - Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns - Clock Uncertainty: 0.000ns - - Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X56Y28.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10> - inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 - SLICE_X28Y62.BY net (fanout=13) 2.537 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10> - SLICE_X28Y62.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 - inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 - ------------------------------------------------- --------------------------- - Total 3.124ns (0.587ns logic, 2.537ns route) - (18.8% logic, 81.2% route) - --------------------------------------------------------------------------------- -Slack: 36.841ns (requirement - (data path - clock path skew + uncertainty)) +Slack: 35.794ns (requirement - (data path - clock path skew + uncertainty)) Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 (FF) Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 (FF) Requirement: 40.000ns - Data Path Delay: 2.936ns (Levels of Logic = 0) - Clock Path Skew: -0.223ns (2.568 - 2.791) + Data Path Delay: 4.039ns (Levels of Logic = 0) + Clock Path Skew: -0.167ns (2.638 - 2.805) Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns Clock Uncertainty: 0.000ns @@ -94,29 +46,77 @@ Slack: 36.841ns (requirement - (data path - clock path skew + u Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X66Y27.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<9> + SLICE_X15Y74.YQ Tcko 0.286 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15> inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 - SLICE_X50Y44.BY net (fanout=13) 2.349 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15> - SLICE_X50Y44.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<15> + SLICE_X54Y45.BY net (fanout=13) 3.473 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15> + SLICE_X54Y45.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<15> inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 ------------------------------------------------- --------------------------- - Total 2.936ns (0.587ns logic, 2.349ns route) - (20.0% logic, 80.0% route) + Total 4.039ns (0.566ns logic, 3.473ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack: 35.912ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_14 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/tag_14 (FF) + Requirement: 40.000ns + Data Path Delay: 3.938ns (Levels of Logic = 0) + Clock Path Skew: -0.150ns (2.642 - 2.792) + Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns + Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_14 to inst_ac97_wb/inst_ac_io/inst_ac_in/tag_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y74.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<14> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_14 + SLICE_X54Y43.BY net (fanout=13) 3.351 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<14> + SLICE_X54Y43.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<14> + inst_ac97_wb/inst_ac_io/inst_ac_in/tag_14 + ------------------------------------------------- --------------------------- + Total 3.938ns (0.587ns logic, 3.351ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- +Slack: 36.239ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_13 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/tag_13 (FF) + Requirement: 40.000ns + Data Path Delay: 3.656ns (Levels of Logic = 0) + Clock Path Skew: -0.105ns (2.645 - 2.750) + Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns + Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_13 to inst_ac97_wb/inst_ac_io/inst_ac_in/tag_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X18Y78.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<13> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_13 + SLICE_X54Y41.BY net (fanout=13) 3.069 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<13> + SLICE_X54Y41.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<13> + inst_ac97_wb/inst_ac_io/inst_ac_in/tag_13 + ------------------------------------------------- --------------------------- + Total 3.656ns (0.587ns logic, 3.069ns route) + (16.1% logic, 83.9% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns HIGH 50%; - 467886 paths analyzed, 11157 endpoints analyzed, 0 failing endpoints + 455768 paths analyzed, 11147 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 9.736ns. + Minimum period is 9.880ns. -------------------------------------------------------------------------------- -Slack: 0.164ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/s_FSM_FFd5 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 (FF) +Slack: 0.020ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r/Mram_RAM (RAM) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/full (FF) Requirement: 9.900ns - Data Path Delay: 9.627ns (Levels of Logic = 8) + Data Path Delay: 9.771ns (Levels of Logic = 7) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 9.900ns @@ -128,50 +128,46 @@ Slack: 0.164ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/full Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X39Y79.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 - inst_vga_frontend/s_FSM_FFd5 - SLICE_X48Y81.F2 net (fanout=50) 1.789 inst_vga_frontend/s_FSM_FFd5 - SLICE_X48Y81.X Tilo 0.195 inst_rom_wb/inst_rom/user_rego<10> - inst_vga_frontend/blitfifo_color_we1_SW0 - SLICE_X49Y96.F3 net (fanout=1) 0.631 N374 - SLICE_X49Y96.X Tilo 0.194 inst_ac97_wb/ACK_O - inst_vga_frontend/blitfifo_color_we1 - SLICE_X55Y122.G4 net (fanout=18) 1.256 inst_vga_frontend/read_cnt_and0000 - SLICE_X55Y122.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<0> - inst_vga_frontend/inst_linefifo/mem_wr_en1 - SLICE_X55Y124.G1 net (fanout=41) 0.638 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/winc - SLICE_X55Y124.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<3>1 - SLICE_X56Y127.G2 net (fanout=3) 0.782 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bnxt_w<3> - SLICE_X56Y127.COUT Topcyg 0.561 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_lut<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> - SLICE_X56Y128.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> - SLICE_X56Y128.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_xor<4> - SLICE_X57Y128.F4 net (fanout=2) 0.396 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_sub0000<4> - SLICE_X57Y128.YMUX Topy 0.777 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_not0000<4>1_INV_0 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_xor<5> - SLICE_X59Y128.F1 net (fanout=1) 1.010 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_addsub0000<5> - SLICE_X59Y128.CLK Tfck 0.235 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_mux0001<5>1 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + RAMB16_X3Y13.DOB19 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r/Mram_RAM + inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r/Mram_RAM + SLICE_X28Y112.F1 net (fanout=3) 1.559 inst_sdram_ctrl_frontend_wb/cat_fifo_dout<19> + SLICE_X28Y112.COUT Topcyf 0.576 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<5> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_lut<4> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<4> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<5> + SLICE_X28Y113.CIN net (fanout=1) 0.000 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<5> + SLICE_X28Y113.XB Tcinxb 0.399 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<6> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<6> + SLICE_X21Y134.F4 net (fanout=8) 1.528 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<6> + SLICE_X21Y134.X Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_6 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/winc74 + SLICE_X19Y154.G1 net (fanout=11) 1.273 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/winc + SLICE_X19Y154.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt<3> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<4>1 + SLICE_X19Y156.G1 net (fanout=2) 0.566 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/bnxt<4> + SLICE_X19Y156.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt<4> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtg<4>1 + SLICE_X19Y156.F3 net (fanout=1) 0.222 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_w<4> + SLICE_X19Y156.X Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt<4> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_full6104 + SLICE_X18Y158.F1 net (fanout=1) 0.557 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_full6104 + SLICE_X18Y158.CLK Tfck 0.215 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/full + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_full6107 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/full ------------------------------------------------- --------------------------- - Total 9.627ns (3.125ns logic, 6.502ns route) - (32.5% logic, 67.5% route) + Total 9.771ns (4.066ns logic, 5.705ns route) + (41.6% logic, 58.4% route) -------------------------------------------------------------------------------- -Slack: 0.202ns (requirement - (data path - clock path skew + uncertainty)) +Slack: 0.134ns (requirement - (data path - clock path skew + uncertainty)) Source: inst_vga_frontend/s_FSM_FFd5 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 (FF) + Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F (RAM) Requirement: 9.900ns - Data Path Delay: 9.589ns (Levels of Logic = 9) + Data Path Delay: 9.657ns (Levels of Logic = 7) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 9.900ns @@ -183,55 +179,44 @@ Slack: 0.202ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X39Y79.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 + SLICE_X45Y73.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 inst_vga_frontend/s_FSM_FFd5 - SLICE_X48Y81.F2 net (fanout=50) 1.789 inst_vga_frontend/s_FSM_FFd5 - SLICE_X48Y81.X Tilo 0.195 inst_rom_wb/inst_rom/user_rego<10> - inst_vga_frontend/blitfifo_color_we1_SW0 - SLICE_X49Y96.F3 net (fanout=1) 0.631 N374 - SLICE_X49Y96.X Tilo 0.194 inst_ac97_wb/ACK_O - inst_vga_frontend/blitfifo_color_we1 - SLICE_X55Y122.G4 net (fanout=18) 1.256 inst_vga_frontend/read_cnt_and0000 - SLICE_X55Y122.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<0> - inst_vga_frontend/inst_linefifo/mem_wr_en1 - SLICE_X55Y122.F3 net (fanout=41) 0.258 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/winc - SLICE_X55Y122.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<0>1 - SLICE_X56Y126.F2 net (fanout=2) 0.758 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bnxt_w<0> - SLICE_X56Y126.COUT Topcyf 0.576 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_lut<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> - SLICE_X56Y127.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> - SLICE_X56Y127.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_xor<2> - SLICE_X57Y127.F3 net (fanout=2) 0.448 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_sub0000<2> - SLICE_X57Y127.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_not0000<2>1_INV_0 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> - SLICE_X57Y128.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> - SLICE_X57Y128.YMUX Tciny 0.503 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_xor<5> - SLICE_X59Y128.F1 net (fanout=1) 1.010 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_addsub0000<5> - SLICE_X59Y128.CLK Tfck 0.235 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_mux0001<5>1 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + SLICE_X44Y73.F4 net (fanout=50) 0.422 inst_vga_frontend/s_FSM_FFd5 + SLICE_X44Y73.X Tilo 0.195 inst_ac97_wb/int_en_tx + inst_vga_frontend/s_FSM_Out61 + SLICE_X37Y67.G4 net (fanout=1) 0.986 inst_vga_frontend/CYC_O_blit_src + SLICE_X37Y67.Y Tilo 0.194 CYC_O + inst_vga_frontend/CYC_O1 + SLICE_X37Y67.F4 net (fanout=7) 0.186 CYC_O_vga + SLICE_X37Y67.X Tilo 0.194 CYC_O + CYC_O1 + SLICE_X37Y68.G4 net (fanout=6) 0.380 CYC_O + SLICE_X37Y68.Y Tilo 0.194 N71 + CYC_I_rom + SLICE_X37Y129.F1 net (fanout=40) 2.228 CYC_I_rom + SLICE_X37Y129.X Tilo 0.194 inst_ps2_wb_1/reg_ps2_tx<1> + MDAT_I<28>23_SW0 + SLICE_X36Y80.G4 net (fanout=1) 1.130 N821 + SLICE_X36Y80.XMUX Tif5x 0.560 MDAT_I<28> + MDAT_I<28>752 + MDAT_I<28>75_f5 + SLICE_X36Y40.BY net (fanout=1) 1.392 MDAT_I<28> + SLICE_X36Y40.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<28> + inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F ------------------------------------------------- --------------------------- - Total 9.589ns (3.439ns logic, 6.150ns route) - (35.9% logic, 64.1% route) + Total 9.657ns (2.933ns logic, 6.724ns route) + (30.4% logic, 69.6% route) -------------------------------------------------------------------------------- -Slack: 0.206ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/s_FSM_FFd5 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 (FF) +Slack: 0.148ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/s_FSM_FFd2 (FF) + Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F (RAM) Requirement: 9.900ns - Data Path Delay: 9.585ns (Levels of Logic = 9) + Data Path Delay: 9.643ns (Levels of Logic = 7) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 9.900ns @@ -243,65 +228,55 @@ Slack: 0.206ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + Maximum Data Path: inst_vga_frontend/s_FSM_FFd2 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X39Y79.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 - inst_vga_frontend/s_FSM_FFd5 - SLICE_X48Y81.F2 net (fanout=50) 1.789 inst_vga_frontend/s_FSM_FFd5 - SLICE_X48Y81.X Tilo 0.195 inst_rom_wb/inst_rom/user_rego<10> - inst_vga_frontend/blitfifo_color_we1_SW0 - SLICE_X49Y96.F3 net (fanout=1) 0.631 N374 - SLICE_X49Y96.X Tilo 0.194 inst_ac97_wb/ACK_O - inst_vga_frontend/blitfifo_color_we1 - SLICE_X55Y122.G4 net (fanout=18) 1.256 inst_vga_frontend/read_cnt_and0000 - SLICE_X55Y122.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<0> - inst_vga_frontend/inst_linefifo/mem_wr_en1 - SLICE_X55Y123.G2 net (fanout=41) 0.365 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/winc - SLICE_X55Y123.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<0>_FRB - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<1>1 - SLICE_X56Y126.G3 net (fanout=3) 0.662 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bnxt_w<1> - SLICE_X56Y126.COUT Topcyg 0.561 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_lut<1> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> - SLICE_X56Y127.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> - SLICE_X56Y127.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_xor<2> - SLICE_X57Y127.F3 net (fanout=2) 0.448 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_sub0000<2> - SLICE_X57Y127.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_not0000<2>1_INV_0 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> - SLICE_X57Y128.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> - SLICE_X57Y128.YMUX Tciny 0.503 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_xor<5> - SLICE_X59Y128.F1 net (fanout=1) 1.010 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_addsub0000<5> - SLICE_X59Y128.CLK Tfck 0.235 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_mux0001<5>1 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + SLICE_X45Y72.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd2 + inst_vga_frontend/s_FSM_FFd2 + SLICE_X44Y73.F3 net (fanout=39) 0.408 inst_vga_frontend/s_FSM_FFd2 + SLICE_X44Y73.X Tilo 0.195 inst_ac97_wb/int_en_tx + inst_vga_frontend/s_FSM_Out61 + SLICE_X37Y67.G4 net (fanout=1) 0.986 inst_vga_frontend/CYC_O_blit_src + SLICE_X37Y67.Y Tilo 0.194 CYC_O + inst_vga_frontend/CYC_O1 + SLICE_X37Y67.F4 net (fanout=7) 0.186 CYC_O_vga + SLICE_X37Y67.X Tilo 0.194 CYC_O + CYC_O1 + SLICE_X37Y68.G4 net (fanout=6) 0.380 CYC_O + SLICE_X37Y68.Y Tilo 0.194 N71 + CYC_I_rom + SLICE_X37Y129.F1 net (fanout=40) 2.228 CYC_I_rom + SLICE_X37Y129.X Tilo 0.194 inst_ps2_wb_1/reg_ps2_tx<1> + MDAT_I<28>23_SW0 + SLICE_X36Y80.G4 net (fanout=1) 1.130 N821 + SLICE_X36Y80.XMUX Tif5x 0.560 MDAT_I<28> + MDAT_I<28>752 + MDAT_I<28>75_f5 + SLICE_X36Y40.BY net (fanout=1) 1.392 MDAT_I<28> + SLICE_X36Y40.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<28> + inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F ------------------------------------------------- --------------------------- - Total 9.585ns (3.424ns logic, 6.161ns route) - (35.7% logic, 64.3% route) + Total 9.643ns (2.933ns logic, 6.710ns route) + (30.4% logic, 69.6% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" 7.5 ns HIGH 50%; - 1844 paths analyzed, 437 endpoints analyzed, 0 failing endpoints + 1810 paths analyzed, 439 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 7.356ns. + Minimum period is 7.348ns. -------------------------------------------------------------------------------- -Slack: 0.072ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_4 (FF) - Requirement: 3.750ns - Data Path Delay: 3.554ns (Levels of Logic = 1) +Slack: 0.152ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) + Requirement: 7.500ns + Data Path Delay: 7.224ns (Levels of Logic = 6) Clock Path Skew: 0.000ns Source Clock: sdram_clk0 rising at 0.000ns - Destination Clock: sdram_clk0 falling at 3.750ns + Destination Clock: sdram_clk0 rising at 7.500ns Clock Uncertainty: 0.124ns Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -310,31 +285,46 @@ Slack: 0.072ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_4 + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X8Y155.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - SLICE_X5Y170.G2 net (fanout=9) 1.258 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - SLICE_X5Y170.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_4_mux00041 - OLOGIC_X0Y182.D1 net (fanout=1) 1.115 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4 - OLOGIC_X0Y182.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<4> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_4 + RAMB16_X0Y16.DOB26 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + SLICE_X7Y135.G1 net (fanout=15) 0.708 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<26> + SLICE_X7Y135.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/Mcount_cycle_cnt_eqn_112 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6_SW0 + SLICE_X6Y138.G2 net (fanout=7) 0.548 N314 + SLICE_X6Y138.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/rinc + SLICE_X6Y138.F4 net (fanout=7) 0.184 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/rinc + SLICE_X6Y138.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<1>1 + SLICE_X6Y141.F1 net (fanout=2) 0.605 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/ptr_r<1> + SLICE_X6Y141.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<1> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<1>1 + SLICE_X6Y140.F3 net (fanout=1) 0.213 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_r<1> + SLICE_X6Y140.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<3> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en31_SW0 + SLICE_X7Y136.G2 net (fanout=2) 0.531 N694 + SLICE_X7Y136.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en_bdd0 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en + RAMB16_X0Y16.ENB net (fanout=1) 0.649 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en + RAMB16_X0Y16.CLKB Trcck_ENB 0.518 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM ------------------------------------------------- --------------------------- - Total 3.554ns (1.181ns logic, 2.373ns route) - (33.2% logic, 66.8% route) + Total 7.224ns (3.786ns logic, 3.438ns route) + (52.4% logic, 47.6% route) -------------------------------------------------------------------------------- -Slack: 0.134ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_rst (FF) - Requirement: 3.750ns - Data Path Delay: 3.492ns (Levels of Logic = 0) +Slack: 0.164ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) + Requirement: 7.500ns + Data Path Delay: 7.212ns (Levels of Logic = 5) Clock Path Skew: 0.000ns Source Clock: sdram_clk0 rising at 0.000ns - Destination Clock: sdram_clk0 falling at 3.750ns + Destination Clock: sdram_clk0 rising at 7.500ns Clock Uncertainty: 0.124ns Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -343,28 +333,43 @@ Slack: 0.134ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_rst + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X19Y125.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg - SLICE_X1Y142.SR net (fanout=7) 2.065 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg - SLICE_X1Y142.CLK Tsrck 1.087 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_rst - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_rst + RAMB16_X0Y16.DOB24 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + SLICE_X6Y134.F3 net (fanout=16) 0.719 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<24> + SLICE_X6Y134.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N111 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cmd_ack21 + SLICE_X6Y136.G1 net (fanout=3) 0.583 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N111 + SLICE_X6Y136.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<5> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<5>_SW0 + SLICE_X6Y142.F1 net (fanout=2) 0.763 N395 + SLICE_X6Y142.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<4> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<4>1 + SLICE_X7Y138.G4 net (fanout=2) 0.511 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_r<4> + SLICE_X7Y138.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<3> + _LC_0_0 + SLICE_X7Y136.G3 net (fanout=1) 0.396 _LC_0_0 + SLICE_X7Y136.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en_bdd0 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en + RAMB16_X0Y16.ENB net (fanout=1) 0.649 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en + RAMB16_X0Y16.CLKB Trcck_ENB 0.518 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM ------------------------------------------------- --------------------------- - Total 3.492ns (1.427ns logic, 2.065ns route) - (40.9% logic, 59.1% route) + Total 7.212ns (3.591ns logic, 3.621ns route) + (49.8% logic, 50.2% route) -------------------------------------------------------------------------------- -Slack: 0.142ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 (FF) - Requirement: 3.750ns - Data Path Delay: 3.484ns (Levels of Logic = 1) +Slack: 0.164ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) + Requirement: 7.500ns + Data Path Delay: 7.212ns (Levels of Logic = 6) Clock Path Skew: 0.000ns Source Clock: sdram_clk0 rising at 0.000ns - Destination Clock: sdram_clk0 falling at 3.750ns + Destination Clock: sdram_clk0 rising at 7.500ns Clock Uncertainty: 0.124ns Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -373,21 +378,36 @@ Slack: 0.142ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X8Y155.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - SLICE_X7Y175.G2 net (fanout=9) 1.403 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - SLICE_X7Y175.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_6_mux00041 - OLOGIC_X0Y188.D1 net (fanout=1) 0.900 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6 - OLOGIC_X0Y188.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<6> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 + RAMB16_X0Y16.DOB24 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + SLICE_X6Y134.F3 net (fanout=16) 0.719 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<24> + SLICE_X6Y134.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N111 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cmd_ack21 + SLICE_X6Y138.G4 net (fanout=3) 0.524 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N111 + SLICE_X6Y138.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/rinc + SLICE_X6Y138.F4 net (fanout=7) 0.184 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/rinc + SLICE_X6Y138.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<1>1 + SLICE_X6Y141.F1 net (fanout=2) 0.605 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/ptr_r<1> + SLICE_X6Y141.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<1> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<1>1 + SLICE_X6Y140.F3 net (fanout=1) 0.213 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_r<1> + SLICE_X6Y140.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<3> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en31_SW0 + SLICE_X7Y136.G2 net (fanout=2) 0.531 N694 + SLICE_X7Y136.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en_bdd0 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en + RAMB16_X0Y16.ENB net (fanout=1) 0.649 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en + RAMB16_X0Y16.CLKB Trcck_ENB 0.518 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM ------------------------------------------------- --------------------------- - Total 3.484ns (1.181ns logic, 2.303ns route) - (33.9% logic, 66.1% route) + Total 7.212ns (3.787ns logic, 3.425ns route) + (52.5% logic, 47.5% route) -------------------------------------------------------------------------------- @@ -397,75 +417,11 @@ Timing constraint: PATH "TS_unrelate_SDRAM_path" TIG; 24 paths analyzed, 22 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) -------------------------------------------------------------------------------- -Delay: 9.446ns (data path - clock path skew + uncertainty) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) - Data Path Delay: 2.928ns (Levels of Logic = 1) - Clock Path Skew: -6.274ns (-2.389 - 3.885) - Source Clock: CLK_O rising - Destination Clock: sdram_clk0 rising - Clock Uncertainty: 0.244ns - - Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.248ns - Phase Error (PE): 0.120ns - - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X15Y164.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X7Y152.G3 net (fanout=20) 1.411 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X7Y152.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 - SLICE_X7Y153.CE net (fanout=1) 0.430 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke - SLICE_X7Y153.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 - ------------------------------------------------- --------------------------- - Total 2.928ns (1.087ns logic, 1.841ns route) - (37.1% logic, 62.9% route) - --------------------------------------------------------------------------------- -Delay: 9.421ns (data path - clock path skew + uncertainty) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) - Data Path Delay: 2.900ns (Levels of Logic = 1) - Clock Path Skew: -6.277ns (-2.389 - 3.888) - Source Clock: CLK_O rising - Destination Clock: sdram_clk0 rising - Clock Uncertainty: 0.244ns - - Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.248ns - Phase Error (PE): 0.120ns - - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X15Y161.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - SLICE_X7Y152.G1 net (fanout=9) 1.383 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - SLICE_X7Y152.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 - SLICE_X7Y153.CE net (fanout=1) 0.430 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke - SLICE_X7Y153.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 - ------------------------------------------------- --------------------------- - Total 2.900ns (1.087ns logic, 1.813ns route) - (37.5% logic, 62.5% route) - --------------------------------------------------------------------------------- -Delay: 8.805ns (data path - clock path skew + uncertainty) +Delay: 9.779ns (data path - clock path skew + uncertainty) Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF) Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF) - Data Path Delay: 2.320ns (Levels of Logic = 2) - Clock Path Skew: -6.241ns (-2.356 - 3.885) + Data Path Delay: 3.255ns (Levels of Logic = 2) + Clock Path Skew: -6.280ns (-2.404 - 3.876) Source Clock: CLK_O rising Destination Clock: sdram_clk0 rising Clock Uncertainty: 0.244ns @@ -480,18 +436,83 @@ Delay: 8.805ns (data path - clock path skew + uncertainty) Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X15Y164.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X13Y175.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X10Y154.F3 net (fanout=20) 1.411 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X10Y154.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/data_reg_r<49> + SLICE_X6Y154.F2 net (fanout=20) 1.559 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X6Y154.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - SLICE_X10Y155.F4 net (fanout=1) 0.159 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - SLICE_X10Y155.CLK Tfck 0.215 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + SLICE_X9Y154.F2 net (fanout=1) 0.926 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + SLICE_X9Y154.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In62 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 ------------------------------------------------- --------------------------- - Total 2.320ns (0.750ns logic, 1.570ns route) - (32.3% logic, 67.7% route) + Total 3.255ns (0.770ns logic, 2.485ns route) + (23.7% logic, 76.3% route) + +-------------------------------------------------------------------------------- +Delay: 9.603ns (data path - clock path skew + uncertainty) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF) + Data Path Delay: 3.061ns (Levels of Logic = 2) + Clock Path Skew: -6.298ns (-2.404 - 3.894) + Source Clock: CLK_O rising + Destination Clock: sdram_clk0 rising + Clock Uncertainty: 0.244ns + + Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.120ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y160.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X6Y154.F1 net (fanout=9) 1.345 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X6Y154.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + SLICE_X9Y154.F2 net (fanout=1) 0.926 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + SLICE_X9Y154.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In62 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + ------------------------------------------------- --------------------------- + Total 3.061ns (0.790ns logic, 2.271ns route) + (25.8% logic, 74.2% route) + +-------------------------------------------------------------------------------- +Delay: 9.343ns (data path - clock path skew + uncertainty) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) + Data Path Delay: 2.824ns (Levels of Logic = 1) + Clock Path Skew: -6.275ns (-2.399 - 3.876) + Source Clock: CLK_O rising + Destination Clock: sdram_clk0 rising + Clock Uncertainty: 0.244ns + + Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.120ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X13Y175.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X5Y155.G3 net (fanout=20) 1.461 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X5Y155.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 + SLICE_X4Y155.CE net (fanout=1) 0.275 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke + SLICE_X4Y155.CLK Tceck 0.554 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + ------------------------------------------------- --------------------------- + Total 2.824ns (1.088ns logic, 1.736ns route) + (38.5% logic, 61.5% route) -------------------------------------------------------------------------------- @@ -500,14 +521,14 @@ Timing constraint: TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 ns HIGH 50%; 14750 paths analyzed, 701 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 7.990ns. + Minimum period is 7.923ns. -------------------------------------------------------------------------------- -Slack: 0.010ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_1 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 (RAM) +Slack: 0.077ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_2 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 (RAM) Requirement: 8.000ns - Data Path Delay: 7.674ns (Levels of Logic = 8) - Clock Path Skew: -0.181ns (2.507 - 2.688) + Data Path Delay: 7.550ns (Levels of Logic = 6) + Clock Path Skew: -0.238ns (0.902 - 1.140) Source Clock: vga_clk rising at 0.000ns Destination Clock: vga_clk rising at 8.000ns Clock Uncertainty: 0.135ns @@ -518,57 +539,49 @@ Slack: 0.010ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.270ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_2 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X54Y140.YQ Tcko 0.360 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_1 - SLICE_X55Y140.G1 net (fanout=3) 0.593 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> - SLICE_X55Y140.COUT Topcyg 0.559 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1>_rt - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> - SLICE_X55Y141.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> - SLICE_X55Y141.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X65Y138.XQ Tcko 0.340 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_2 + SLICE_X64Y139.F1 net (fanout=3) 0.581 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<2> + SLICE_X64Y139.COUT Topcyf 0.576 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<2>_rt inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<2> inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - SLICE_X55Y142.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - SLICE_X55Y142.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/empty - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> - SLICE_X55Y143.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> - SLICE_X55Y143.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<6> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7> - SLICE_X55Y144.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7> - SLICE_X55Y144.YMUX Tciny 0.503 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<8> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<9> - SLICE_X53Y142.G2 net (fanout=1) 1.221 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<9> - SLICE_X53Y142.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<9>1 - SLICE_X53Y139.G2 net (fanout=10) 0.546 inst_vga_frontend/inst_linefifo/ptr_r<9> - SLICE_X53Y139.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<9>1 - SLICE_X53Y138.F1 net (fanout=1) 0.387 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<9> - SLICE_X53Y138.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/pre_empty - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<4> + SLICE_X64Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X64Y140.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<4> + SLICE_X65Y143.F1 net (fanout=1) 1.040 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<4> + SLICE_X65Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<4>1 + SLICE_X67Y138.F2 net (fanout=10) 0.725 inst_vga_frontend/inst_linefifo/ptr_r<4> + SLICE_X67Y138.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<4>1 + SLICE_X61Y139.F3 net (fanout=1) 0.815 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<4> + SLICE_X61Y139.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X61Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X61Y140.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> - RAMB16_X4Y15.ENB net (fanout=8) 1.768 inst_vga_frontend/inst_linefifo/pre_empty - RAMB16_X4Y15.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 - inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + RAMB16_X4Y16.ENB net (fanout=8) 1.473 inst_vga_frontend/inst_linefifo/pre_empty + RAMB16_X4Y16.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 + inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 ------------------------------------------------- --------------------------- - Total 7.674ns (3.159ns logic, 4.515ns route) - (41.2% logic, 58.8% route) + Total 7.550ns (2.916ns logic, 4.634ns route) + (38.6% logic, 61.4% route) -------------------------------------------------------------------------------- -Slack: 0.017ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 (RAM) +Slack: 0.105ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_0 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 (RAM) Requirement: 8.000ns - Data Path Delay: 7.631ns (Levels of Logic = 7) - Clock Path Skew: -0.217ns (2.507 - 2.724) + Data Path Delay: 7.518ns (Levels of Logic = 7) + Clock Path Skew: -0.242ns (0.902 - 1.144) Source Clock: vga_clk rising at 0.000ns Destination Clock: vga_clk rising at 8.000ns Clock Uncertainty: 0.135ns @@ -579,51 +592,53 @@ Slack: 0.017ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.270ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_0 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X61Y168.XQ Tcko 0.340 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 - inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 - SLICE_X56Y156.F3 net (fanout=8) 0.863 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 - SLICE_X56Y156.X Tilo 0.195 inst_vga_frontend/stat_scan - inst_vga_frontend/inst_vga_backend/is_scan1 - SLICE_X54Y144.G2 net (fanout=17) 0.826 inst_vga_frontend/stat_scan - SLICE_X54Y144.Y Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<11> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/rinc1 - SLICE_X53Y143.F4 net (fanout=12) 0.455 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/rinc - SLICE_X53Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 - SLICE_X54Y140.F1 net (fanout=9) 0.607 inst_vga_frontend/inst_linefifo/ptr_r<0> - SLICE_X54Y140.X Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<0>1 - SLICE_X53Y136.F2 net (fanout=1) 0.730 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<0> - SLICE_X53Y136.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> - SLICE_X53Y137.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> - SLICE_X53Y137.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X65Y136.XQ Tcko 0.340 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_0 + SLICE_X64Y138.F3 net (fanout=3) 0.460 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> + SLICE_X64Y138.COUT Topcyf 0.576 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_lut<0>_INV_0 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> + SLICE_X64Y139.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> + SLICE_X64Y139.COUT Tbyp 0.089 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X64Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X64Y140.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<4> + SLICE_X65Y143.F1 net (fanout=1) 1.040 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<4> + SLICE_X65Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<4>1 + SLICE_X67Y138.F2 net (fanout=10) 0.725 inst_vga_frontend/inst_linefifo/ptr_r<4> + SLICE_X67Y138.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<4>1 + SLICE_X61Y139.F3 net (fanout=1) 0.815 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<4> + SLICE_X61Y139.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<2> inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X53Y138.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X53Y138.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty + SLICE_X61Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X61Y140.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> - RAMB16_X4Y15.ENB net (fanout=8) 1.768 inst_vga_frontend/inst_linefifo/pre_empty - RAMB16_X4Y15.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 - inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + RAMB16_X4Y16.ENB net (fanout=8) 1.473 inst_vga_frontend/inst_linefifo/pre_empty + RAMB16_X4Y16.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 + inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 ------------------------------------------------- --------------------------- - Total 7.631ns (2.382ns logic, 5.249ns route) - (31.2% logic, 68.8% route) + Total 7.518ns (3.005ns logic, 4.513ns route) + (40.0% logic, 60.0% route) -------------------------------------------------------------------------------- -Slack: 0.020ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 (RAM) +Slack: 0.107ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_3 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 (RAM) Requirement: 8.000ns - Data Path Delay: 7.609ns (Levels of Logic = 7) - Clock Path Skew: -0.236ns (2.507 - 2.743) + Data Path Delay: 7.520ns (Levels of Logic = 6) + Clock Path Skew: -0.238ns (0.902 - 1.140) Source Clock: vga_clk rising at 0.000ns Destination Clock: vga_clk rising at 8.000ns Clock Uncertainty: 0.135ns @@ -634,43 +649,40 @@ Slack: 0.020ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.270ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_3 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X62Y161.XQ Tcko 0.360 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 - inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 - SLICE_X56Y156.F4 net (fanout=9) 0.821 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 - SLICE_X56Y156.X Tilo 0.195 inst_vga_frontend/stat_scan - inst_vga_frontend/inst_vga_backend/is_scan1 - SLICE_X54Y144.G2 net (fanout=17) 0.826 inst_vga_frontend/stat_scan - SLICE_X54Y144.Y Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<11> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/rinc1 - SLICE_X53Y143.F4 net (fanout=12) 0.455 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/rinc - SLICE_X53Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 - SLICE_X54Y140.F1 net (fanout=9) 0.607 inst_vga_frontend/inst_linefifo/ptr_r<0> - SLICE_X54Y140.X Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<0>1 - SLICE_X53Y136.F2 net (fanout=1) 0.730 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<0> - SLICE_X53Y136.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> - SLICE_X53Y137.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> - SLICE_X53Y137.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X65Y138.YQ Tcko 0.340 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_3 + SLICE_X64Y139.G2 net (fanout=3) 0.566 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<3> + SLICE_X64Y139.COUT Topcyg 0.561 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<3>_rt + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X64Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X64Y140.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<4> + SLICE_X65Y143.F1 net (fanout=1) 1.040 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<4> + SLICE_X65Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<4>1 + SLICE_X67Y138.F2 net (fanout=10) 0.725 inst_vga_frontend/inst_linefifo/ptr_r<4> + SLICE_X67Y138.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<4>1 + SLICE_X61Y139.F3 net (fanout=1) 0.815 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<4> + SLICE_X61Y139.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<2> inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X53Y138.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X53Y138.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty + SLICE_X61Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X61Y140.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> - RAMB16_X4Y15.ENB net (fanout=8) 1.768 inst_vga_frontend/inst_linefifo/pre_empty - RAMB16_X4Y15.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 - inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + RAMB16_X4Y16.ENB net (fanout=8) 1.473 inst_vga_frontend/inst_linefifo/pre_empty + RAMB16_X4Y16.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 + inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 ------------------------------------------------- --------------------------- - Total 7.609ns (2.402ns logic, 5.207ns route) - (31.6% logic, 68.4% route) + Total 7.520ns (2.901ns logic, 4.619ns route) + (38.6% logic, 61.4% route) -------------------------------------------------------------------------------- @@ -680,10 +692,10 @@ Timing constraint: PATH "TS_unrelate_VGA_path" TIG; 64 paths analyzed, 64 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) -------------------------------------------------------------------------------- -Delay: 6.486ns (data path - clock path skew + uncertainty) +Delay: 6.002ns (data path - clock path skew + uncertainty) Source: inst_vga_frontend/cg_color_2_6 (FF) Destination: inst_vga_frontend/inst_vga_backend/vga_blue_6 (FF) - Data Path Delay: 5.945ns (Levels of Logic = 1) + Data Path Delay: 5.461ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: CLK_O rising Destination Clock: vga_clk rising @@ -699,23 +711,23 @@ Delay: 6.486ns (data path - clock path skew + uncertainty) Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X42Y102.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_3 + SLICE_X50Y118.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_6 inst_vga_frontend/cg_color_2_6 - SLICE_X65Y148.G2 net (fanout=2) 2.455 inst_vga_frontend/cg_color_2_6 - SLICE_X65Y148.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 + SLICE_X67Y150.G4 net (fanout=2) 1.983 inst_vga_frontend/cg_color_2_6 + SLICE_X67Y150.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 - OLOGIC_X2Y172.REV net (fanout=1) 1.639 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 + OLOGIC_X2Y172.REV net (fanout=1) 1.627 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 OLOGIC_X2Y172.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<6> inst_vga_frontend/inst_vga_backend/vga_blue_6 ------------------------------------------------- --------------------------- - Total 5.945ns (1.851ns logic, 4.094ns route) - (31.1% logic, 68.9% route) + Total 5.461ns (1.851ns logic, 3.610ns route) + (33.9% logic, 66.1% route) -------------------------------------------------------------------------------- -Delay: 6.242ns (data path - clock path skew + uncertainty) - Source: inst_vga_frontend/cg_color_2_3 (FF) - Destination: inst_vga_frontend/inst_vga_backend/vga_blue_3 (FF) - Data Path Delay: 5.701ns (Levels of Logic = 1) +Delay: 5.938ns (data path - clock path skew + uncertainty) + Source: inst_vga_frontend/cg_color_1_5 (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_green_5 (FF) + Data Path Delay: 5.397ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: CLK_O rising Destination Clock: vga_clk rising @@ -727,27 +739,27 @@ Delay: 6.242ns (data path - clock path skew + uncertainty) Discrete Jitter (DJ): 0.347ns Phase Error (PE): 0.367ns - Maximum Data Path: inst_vga_frontend/cg_color_2_3 to inst_vga_frontend/inst_vga_backend/vga_blue_3 + Maximum Data Path: inst_vga_frontend/cg_color_1_5 to inst_vga_frontend/inst_vga_backend/vga_green_5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X42Y102.XQ Tcko 0.360 inst_vga_frontend/cg_color_2_3 - inst_vga_frontend/cg_color_2_3 - SLICE_X65Y146.G1 net (fanout=2) 2.369 inst_vga_frontend/cg_color_2_3 - SLICE_X65Y146.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<3>0 - inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<3>0 - OLOGIC_X2Y169.REV net (fanout=1) 1.481 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<3>0 - OLOGIC_X2Y169.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<3> - inst_vga_frontend/inst_vga_backend/vga_blue_3 + SLICE_X49Y106.YQ Tcko 0.340 inst_vga_frontend/cg_color_1_5 + inst_vga_frontend/cg_color_1_5 + SLICE_X69Y134.G1 net (fanout=2) 2.365 inst_vga_frontend/cg_color_1_5 + SLICE_X69Y134.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_green_mux0003<5>0 + inst_vga_frontend/inst_vga_backend/vga_green_mux0003<5>0 + OLOGIC_X2Y150.REV net (fanout=1) 1.201 inst_vga_frontend/inst_vga_backend/vga_green_mux0003<5>0 + OLOGIC_X2Y150.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_green<5> + inst_vga_frontend/inst_vga_backend/vga_green_5 ------------------------------------------------- --------------------------- - Total 5.701ns (1.851ns logic, 3.850ns route) - (32.5% logic, 67.5% route) + Total 5.397ns (1.831ns logic, 3.566ns route) + (33.9% logic, 66.1% route) -------------------------------------------------------------------------------- -Delay: 6.202ns (data path - clock path skew + uncertainty) - Source: inst_vga_frontend/cg_color_2_4 (FF) - Destination: inst_vga_frontend/inst_vga_backend/vga_blue_4 (FF) - Data Path Delay: 5.661ns (Levels of Logic = 1) +Delay: 5.936ns (data path - clock path skew + uncertainty) + Source: inst_vga_frontend/cg_color_2_5 (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_blue_5 (FF) + Data Path Delay: 5.395ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: CLK_O rising Destination Clock: vga_clk rising @@ -759,501 +771,314 @@ Delay: 6.202ns (data path - clock path skew + uncertainty) Discrete Jitter (DJ): 0.347ns Phase Error (PE): 0.367ns - Maximum Data Path: inst_vga_frontend/cg_color_2_4 to inst_vga_frontend/inst_vga_backend/vga_blue_4 + Maximum Data Path: inst_vga_frontend/cg_color_2_5 to inst_vga_frontend/inst_vga_backend/vga_blue_5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X44Y106.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_4 - inst_vga_frontend/cg_color_2_4 - SLICE_X64Y146.G1 net (fanout=2) 2.349 inst_vga_frontend/cg_color_2_4 - SLICE_X64Y146.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<4>0 - inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<4>0 - OLOGIC_X2Y170.REV net (fanout=1) 1.460 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<4>0 - OLOGIC_X2Y170.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<4> - inst_vga_frontend/inst_vga_backend/vga_blue_4 + SLICE_X52Y117.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_5 + inst_vga_frontend/cg_color_2_5 + SLICE_X68Y150.F1 net (fanout=2) 2.252 inst_vga_frontend/cg_color_2_5 + SLICE_X68Y150.X Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar<4> + inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 + OLOGIC_X2Y171.REV net (fanout=1) 1.291 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 + OLOGIC_X2Y171.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<5> + inst_vga_frontend/inst_vga_backend/vga_blue_5 ------------------------------------------------- --------------------------- - Total 5.661ns (1.852ns logic, 3.809ns route) - (32.7% logic, 67.3% route) + Total 5.395ns (1.852ns logic, 3.543ns route) + (34.3% logic, 65.7% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 ns HIGH 50%; - 852048 paths analyzed, 11745 endpoints analyzed, 5 failing endpoints - 5 timing errors detected. (5 setup errors, 0 hold errors) - Minimum period is 10.018ns. --------------------------------------------------------------------------------- -Slack: -0.118ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 (FF) - Destination: inst_mips_top/inst_pipeline/pc.nxt_25 (FF) - Requirement: 9.900ns - Data Path Delay: 9.875ns (Levels of Logic = 23) - Clock Path Skew: -0.083ns (2.876 - 2.959) - Source Clock: cpu_clk rising at 0.000ns - Destination Clock: cpu_clk rising at 9.900ns - Clock Uncertainty: 0.060ns - - Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.120ns - Phase Error (PE): 0.000ns - - Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 to inst_mips_top/inst_pipeline/pc.nxt_25 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X12Y12.XQ Tcko 0.360 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 - inst_mips_top/inst_pipeline/EX_stage.reg_a_0 - SLICE_X13Y10.F2 net (fanout=8) 0.817 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 - SLICE_X13Y10.COUT Topcyf 0.573 inst_mips_top/inst_biu/DAT_I_dmem_rd<23> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X13Y11.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X13Y11.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<22> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X13Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X13Y12.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/bcu_op_b<8> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X13Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X13Y13.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X13Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X13Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_b_27 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X13Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X13Y15.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X13Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X13Y16.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<31> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X13Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X13Y17.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_2 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X13Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X13Y18.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_12 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X13Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X13Y19.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<30> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X13Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X13Y20.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X13Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X13Y21.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<12> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X13Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X13Y22.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X13Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X13Y23.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<4> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X13Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X13Y24.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X13Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X13Y25.YMUX Tciny 0.503 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> - SLICE_X16Y36.F4 net (fanout=4) 1.115 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> - SLICE_X16Y36.X Tilo 0.195 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_uvf - inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf - SLICE_X20Y34.G4 net (fanout=1) 0.535 inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf - SLICE_X20Y34.Y Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - inst_mips_top/inst_pipeline/EX_stage_exc23 - SLICE_X20Y34.F4 net (fanout=17) 0.183 inst_mips_top/inst_pipeline/EX_stage_exc - SLICE_X20Y34.X Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - inst_mips_top/inst_pipeline/sdu_ID_nop - SLICE_X22Y34.G4 net (fanout=15) 0.375 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - SLICE_X22Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 - inst_mips_top/inst_cop/cop_pipe_ID_RFE31 - SLICE_X24Y34.G4 net (fanout=6) 0.428 inst_mips_top/inst_cop/cop_pipe_ID_RFE - SLICE_X24Y34.Y Tilo 0.195 inst_mips_top/inst_pipeline/pc.pc_branch_1 - inst_mips_top/inst_pipeline/sdu_ID_stall_SW0 - SLICE_X27Y35.G4 net (fanout=2) 0.330 inst_mips_top/N178 - SLICE_X27Y35.Y Tilo 0.194 inst_mips_top/inst_cop/exc_state_FSM_FFd6 - inst_mips_top/inst_pipeline/sdu_ID_stall - SLICE_X19Y31.F4 net (fanout=4) 0.824 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_stall - SLICE_X19Y31.X Tilo 0.194 inst_mips_top/inst_pipeline/pc_nxt_not0001 - inst_mips_top/inst_pipeline/pc_nxt_not00011 - SLICE_X18Y38.CE net (fanout=32) 0.711 inst_mips_top/inst_pipeline/pc_nxt_not0001 - SLICE_X18Y38.CLK Tceck 0.554 inst_mips_top/inst_pipeline/pc.nxt_25 - inst_mips_top/inst_pipeline/pc.nxt_25 - ------------------------------------------------- --------------------------- - Total 9.875ns (4.557ns logic, 5.318ns route) - (46.1% logic, 53.9% route) - --------------------------------------------------------------------------------- -Slack: -0.115ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 (FF) - Destination: inst_mips_top/inst_pipeline/pc.nxt_7 (FF) - Requirement: 9.900ns - Data Path Delay: 9.867ns (Levels of Logic = 23) - Clock Path Skew: -0.088ns (2.871 - 2.959) - Source Clock: cpu_clk rising at 0.000ns - Destination Clock: cpu_clk rising at 9.900ns - Clock Uncertainty: 0.060ns - - Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.120ns - Phase Error (PE): 0.000ns - - Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 to inst_mips_top/inst_pipeline/pc.nxt_7 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X12Y12.XQ Tcko 0.360 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 - inst_mips_top/inst_pipeline/EX_stage.reg_a_0 - SLICE_X13Y10.F2 net (fanout=8) 0.817 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 - SLICE_X13Y10.COUT Topcyf 0.573 inst_mips_top/inst_biu/DAT_I_dmem_rd<23> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X13Y11.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X13Y11.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<22> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X13Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X13Y12.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/bcu_op_b<8> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X13Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X13Y13.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X13Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X13Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_b_27 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X13Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X13Y15.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X13Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X13Y16.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<31> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X13Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X13Y17.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_2 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X13Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X13Y18.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_12 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X13Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X13Y19.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<30> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X13Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X13Y20.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X13Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X13Y21.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<12> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X13Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X13Y22.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X13Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X13Y23.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<4> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X13Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X13Y24.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X13Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X13Y25.YMUX Tciny 0.503 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> - SLICE_X16Y36.F4 net (fanout=4) 1.115 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> - SLICE_X16Y36.X Tilo 0.195 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_uvf - inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf - SLICE_X20Y34.G4 net (fanout=1) 0.535 inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf - SLICE_X20Y34.Y Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - inst_mips_top/inst_pipeline/EX_stage_exc23 - SLICE_X20Y34.F4 net (fanout=17) 0.183 inst_mips_top/inst_pipeline/EX_stage_exc - SLICE_X20Y34.X Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - inst_mips_top/inst_pipeline/sdu_ID_nop - SLICE_X22Y34.G4 net (fanout=15) 0.375 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - SLICE_X22Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 - inst_mips_top/inst_cop/cop_pipe_ID_RFE31 - SLICE_X24Y34.G4 net (fanout=6) 0.428 inst_mips_top/inst_cop/cop_pipe_ID_RFE - SLICE_X24Y34.Y Tilo 0.195 inst_mips_top/inst_pipeline/pc.pc_branch_1 - inst_mips_top/inst_pipeline/sdu_ID_stall_SW0 - SLICE_X27Y35.G4 net (fanout=2) 0.330 inst_mips_top/N178 - SLICE_X27Y35.Y Tilo 0.194 inst_mips_top/inst_cop/exc_state_FSM_FFd6 - inst_mips_top/inst_pipeline/sdu_ID_stall - SLICE_X19Y31.F4 net (fanout=4) 0.824 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_stall - SLICE_X19Y31.X Tilo 0.194 inst_mips_top/inst_pipeline/pc_nxt_not0001 - inst_mips_top/inst_pipeline/pc_nxt_not00011 - SLICE_X20Y37.CE net (fanout=32) 0.703 inst_mips_top/inst_pipeline/pc_nxt_not0001 - SLICE_X20Y37.CLK Tceck 0.554 inst_mips_top/inst_pipeline/pc.nxt_7 - inst_mips_top/inst_pipeline/pc.nxt_7 - ------------------------------------------------- --------------------------- - Total 9.867ns (4.557ns logic, 5.310ns route) - (46.2% logic, 53.8% route) - --------------------------------------------------------------------------------- -Slack: -0.098ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 (FF) - Destination: inst_mips_top/inst_pipeline/pc.nxt_6 (FF) - Requirement: 9.900ns - Data Path Delay: 9.855ns (Levels of Logic = 23) - Clock Path Skew: -0.083ns (1.216 - 1.299) - Source Clock: cpu_clk rising at 0.000ns - Destination Clock: cpu_clk rising at 9.900ns - Clock Uncertainty: 0.060ns - - Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.120ns - Phase Error (PE): 0.000ns - - Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 to inst_mips_top/inst_pipeline/pc.nxt_6 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X12Y12.XQ Tcko 0.360 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 - inst_mips_top/inst_pipeline/EX_stage.reg_a_0 - SLICE_X13Y10.F2 net (fanout=8) 0.817 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 - SLICE_X13Y10.COUT Topcyf 0.573 inst_mips_top/inst_biu/DAT_I_dmem_rd<23> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X13Y11.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X13Y11.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<22> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X13Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X13Y12.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/bcu_op_b<8> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X13Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X13Y13.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X13Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X13Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_b_27 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X13Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X13Y15.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X13Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X13Y16.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<31> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X13Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X13Y17.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_2 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X13Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X13Y18.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_12 - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X13Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X13Y19.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<30> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X13Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X13Y20.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X13Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X13Y21.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<12> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X13Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X13Y22.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X13Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X13Y23.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<4> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X13Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X13Y24.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X13Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X13Y25.YMUX Tciny 0.503 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> - SLICE_X16Y36.F4 net (fanout=4) 1.115 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> - SLICE_X16Y36.X Tilo 0.195 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_uvf - inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf - SLICE_X20Y34.G4 net (fanout=1) 0.535 inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf - SLICE_X20Y34.Y Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - inst_mips_top/inst_pipeline/EX_stage_exc23 - SLICE_X20Y34.F4 net (fanout=17) 0.183 inst_mips_top/inst_pipeline/EX_stage_exc - SLICE_X20Y34.X Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - inst_mips_top/inst_pipeline/sdu_ID_nop - SLICE_X22Y34.G4 net (fanout=15) 0.375 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - SLICE_X22Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 - inst_mips_top/inst_cop/cop_pipe_ID_RFE31 - SLICE_X24Y34.G4 net (fanout=6) 0.428 inst_mips_top/inst_cop/cop_pipe_ID_RFE - SLICE_X24Y34.Y Tilo 0.195 inst_mips_top/inst_pipeline/pc.pc_branch_1 - inst_mips_top/inst_pipeline/sdu_ID_stall_SW0 - SLICE_X27Y35.G4 net (fanout=2) 0.330 inst_mips_top/N178 - SLICE_X27Y35.Y Tilo 0.194 inst_mips_top/inst_cop/exc_state_FSM_FFd6 - inst_mips_top/inst_pipeline/sdu_ID_stall - SLICE_X19Y31.F4 net (fanout=4) 0.824 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_stall - SLICE_X19Y31.X Tilo 0.194 inst_mips_top/inst_pipeline/pc_nxt_not0001 - inst_mips_top/inst_pipeline/pc_nxt_not00011 - SLICE_X18Y19.CE net (fanout=32) 0.691 inst_mips_top/inst_pipeline/pc_nxt_not0001 - SLICE_X18Y19.CLK Tceck 0.554 inst_mips_top/inst_pipeline/pc.nxt_6 - inst_mips_top/inst_pipeline/pc.nxt_6 - ------------------------------------------------- --------------------------- - Total 9.855ns (4.557ns logic, 5.298ns route) - (46.2% logic, 53.8% route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: PATH "TS_unrelate_CPU_path" TIG; - - 58068 paths analyzed, 854 endpoints analyzed, 0 failing endpoints + 857751 paths analyzed, 11767 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum period is 9.899ns. -------------------------------------------------------------------------------- -Delay: 8.192ns (data path) - Source: arb_gnt_0 (FF) - Destination: inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM64.SLICEM_F (RAM) - Data Path Delay: 8.192ns (Levels of Logic = 7) - Source Clock: CLK_O rising at 0.000ns +Slack: 0.001ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram/Mram_RAM1 (RAM) + Destination: inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 (FF) + Requirement: 9.900ns + Data Path Delay: 9.839ns (Levels of Logic = 8) + Clock Path Skew: 0.000ns + Source Clock: cpu_clk rising at 0.000ns + Destination Clock: cpu_clk rising at 9.900ns + Clock Uncertainty: 0.060ns - Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM64.SLICEM_F + Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.120ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram/Mram_RAM1 to inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X36Y67.XQ Tcko 0.360 arb_gnt<0> - arb_gnt_0 - SLICE_X34Y65.G1 net (fanout=114) 1.226 arb_gnt<0> - SLICE_X34Y65.Y Tilo 0.195 inst_flash_port/ADDR_I_r<16> - Mmux_ADDR_O251 - SLICE_X37Y67.G2 net (fanout=6) 0.930 ADDR_O<31> - SLICE_X37Y67.Y Tilo 0.194 SRDY_O_sdram - CYC_I_sdram_1 - SLICE_X37Y67.F4 net (fanout=1) 0.159 CYC_I_sdram_1/O - SLICE_X37Y67.X Tilo 0.194 SRDY_O_sdram - inst_sdram_ctrl_frontend_wb/rdy1 - SLICE_X39Y65.F3 net (fanout=6) 0.424 SRDY_O_sdram - SLICE_X39Y65.X Tilo 0.194 SRDY_I26 - SRDY_I26 - SLICE_X35Y51.G4 net (fanout=1) 0.581 SRDY_I26 - SLICE_X35Y51.Y Tilo 0.194 ADDR_O_cpu<31> - SRDY_I36 - SLICE_X35Y50.F1 net (fanout=7) 0.418 SRDY_I - SLICE_X35Y50.X Tilo 0.194 ADDR_O_cpu<16> - SRDY_I_cpu - SLICE_X33Y48.F1 net (fanout=1) 0.799 SRDY_I_cpu - SLICE_X33Y48.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> - inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 - SLICE_X30Y34.F1 net (fanout=67) 1.936 inst_mips_top/inst_biu/inst_bout_fifo/ptr_r<0> + RAMB16_X2Y0.DOB1 Trcko_DOWB 2.100 inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram/Mram_RAM1 + inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram/Mram_RAM1 + SLICE_X16Y7.G3 net (fanout=1) 0.911 inst_mips_top/inst_biu/dcache_dout<17> + SLICE_X16Y7.Y Tilo 0.195 inst_mips_top/inst_cop/test_reg<17> + inst_mips_top/inst_biu/cpu_dmem_din<17>1 + SLICE_X14Y11.F3 net (fanout=4) 0.672 inst_mips_top/dmem_din<17> + SLICE_X14Y11.X Tilo 0.195 inst_mips_top/inst_pipeline/bcu_op_b<4> + inst_mips_top/inst_pipeline/stage10_mux0000<17>1 + SLICE_X21Y11.G2 net (fanout=2) 0.821 inst_mips_top/inst_pipeline/stage10_mux0000<17> + SLICE_X21Y11.Y Tilo 0.194 inst_mips_top/inst_pipeline/WB_stage.data_1 + inst_mips_top/inst_pipeline/data4_1_mux000223 + SLICE_X21Y11.F4 net (fanout=1) 0.159 inst_mips_top/inst_pipeline/data4_1_mux000223/O + SLICE_X21Y11.X Tilo 0.194 inst_mips_top/inst_pipeline/WB_stage.data_1 + inst_mips_top/inst_pipeline/data4_1_mux000227 + SLICE_X17Y8.G1 net (fanout=4) 1.320 inst_mips_top/inst_pipeline/MEM_stage_data<1> + SLICE_X17Y8.XMUX Tif5x 0.574 inst_mips_top/inst_pipeline/EX_stage.reg_a_1 + inst_mips_top/inst_pipeline/ID_stage_reg_a<1>68_F + inst_mips_top/inst_pipeline/ID_stage_reg_a<1>68 + SLICE_X6Y7.G4 net (fanout=3) 0.998 inst_mips_top/inst_pipeline/ID_stage_reg_a<1> + SLICE_X6Y7.Y Tilo 0.195 inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000 + inst_mips_top/inst_pipeline/data3_mux0000<1>1 + SLICE_X6Y8.G4 net (fanout=5) 0.400 inst_mips_top/inst_pipeline/data3_mux0000<1> + SLICE_X6Y8.Y Tilo 0.195 inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 + inst_mips_top/inst_pipeline/Madd_EX_stage.shift_ctrl.shamt_rnd_addsub0000_cy<2>11_SW0 + SLICE_X6Y8.F2 net (fanout=1) 0.501 inst_mips_top/inst_pipeline/Madd_EX_stage.shift_ctrl.shamt_rnd_addsub0000_cy<2>11_SW0/O + SLICE_X6Y8.CLK Tfck 0.215 inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 + inst_mips_top/inst_pipeline/EX_stage_shift_ctrl_shamt_rnd_mux0001<3>1 + inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 ------------------------------------------------- --------------------------- - Total 8.192ns (1.719ns logic, 6.473ns route) - (21.0% logic, 79.0% route) + Total 9.839ns (4.057ns logic, 5.782ns route) + (41.2% logic, 58.8% route) -------------------------------------------------------------------------------- -Delay: 8.137ns (data path) - Source: arb_gnt_0 (FF) - Destination: inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F (RAM) - Data Path Delay: 8.137ns (Levels of Logic = 7) - Source Clock: CLK_O rising at 0.000ns +Slack: 0.010ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 (FF) + Destination: inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 (RAM) + Requirement: 9.900ns + Data Path Delay: 9.556ns (Levels of Logic = 23) + Clock Path Skew: -0.274ns (2.666 - 2.940) + Source Clock: cpu_clk rising at 0.000ns + Destination Clock: cpu_clk rising at 9.900ns + Clock Uncertainty: 0.060ns - Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F + Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.120ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 to inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X36Y67.XQ Tcko 0.360 arb_gnt<0> - arb_gnt_0 - SLICE_X34Y65.G1 net (fanout=114) 1.226 arb_gnt<0> - SLICE_X34Y65.Y Tilo 0.195 inst_flash_port/ADDR_I_r<16> - Mmux_ADDR_O251 - SLICE_X37Y67.G2 net (fanout=6) 0.930 ADDR_O<31> - SLICE_X37Y67.Y Tilo 0.194 SRDY_O_sdram - CYC_I_sdram_1 - SLICE_X37Y67.F4 net (fanout=1) 0.159 CYC_I_sdram_1/O - SLICE_X37Y67.X Tilo 0.194 SRDY_O_sdram - inst_sdram_ctrl_frontend_wb/rdy1 - SLICE_X39Y65.F3 net (fanout=6) 0.424 SRDY_O_sdram - SLICE_X39Y65.X Tilo 0.194 SRDY_I26 - SRDY_I26 - SLICE_X35Y51.G4 net (fanout=1) 0.581 SRDY_I26 - SLICE_X35Y51.Y Tilo 0.194 ADDR_O_cpu<31> - SRDY_I36 - SLICE_X35Y50.F1 net (fanout=7) 0.418 SRDY_I - SLICE_X35Y50.X Tilo 0.194 ADDR_O_cpu<16> - SRDY_I_cpu - SLICE_X33Y48.F1 net (fanout=1) 0.799 SRDY_I_cpu - SLICE_X33Y48.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> - inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 - SLICE_X32Y36.F1 net (fanout=67) 1.881 inst_mips_top/inst_biu/inst_bout_fifo/ptr_r<0> + SLICE_X17Y13.YQ Tcko 0.340 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 + inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 + SLICE_X16Y11.F2 net (fanout=12) 0.783 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 + SLICE_X16Y11.COUT Topcyf 0.576 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X16Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X16Y12.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X16Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X16Y13.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X16Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X16Y14.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<6> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X16Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X16Y15.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X16Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X16Y16.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<0> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X16Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X16Y17.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<6> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X16Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X16Y18.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<3> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X16Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X16Y19.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X16Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X16Y20.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<9> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X16Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X16Y21.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X16Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X16Y22.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X16Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X16Y23.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X16Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X16Y24.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X16Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X16Y25.COUT Tbyp 0.089 inst_mips_top/inst_biu/inst_dcache/tag_reg<5> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X16Y26.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X16Y26.YMUX Tciny 0.513 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> + SLICE_X14Y31.F2 net (fanout=4) 0.968 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> + SLICE_X14Y31.X Tilo 0.195 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_uvf + inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf + SLICE_X13Y32.G4 net (fanout=1) 0.371 inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf + SLICE_X13Y32.Y Tilo 0.194 inst_mips_top/RST_I_shift3 + inst_mips_top/inst_pipeline/EX_stage_exc23 + SLICE_X13Y32.F3 net (fanout=17) 0.245 inst_mips_top/inst_pipeline/EX_stage_exc + SLICE_X13Y32.X Tilo 0.194 inst_mips_top/RST_I_shift3 + inst_mips_top/inst_pipeline/sdu_ID_nop + SLICE_X14Y34.G4 net (fanout=15) 0.405 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + SLICE_X14Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 + inst_mips_top/inst_cop/cop_pipe_ID_RFE31 + SLICE_X14Y34.F4 net (fanout=6) 0.169 inst_mips_top/inst_cop/cop_pipe_ID_RFE + SLICE_X14Y34.X Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 + inst_mips_top/inst_cop/ctrl_out_exc_commit11 + SLICE_X16Y34.G2 net (fanout=1) 0.583 inst_mips_top/inst_cop/exc_state_FSM_FFd3-In + SLICE_X16Y34.Y Tilo 0.195 inst_mips_top/inst_biu/inst_icache/cache_req + inst_mips_top/inst_pipeline/imem_en47 + SLICE_X16Y34.F4 net (fanout=2) 0.164 inst_mips_top/imem_en + SLICE_X16Y34.X Tilo 0.195 inst_mips_top/inst_biu/inst_icache/cache_req + inst_mips_top/inst_biu/inst_icache/ram_read_en1 + RAMB16_X3Y6.ENB net (fanout=18) 1.312 inst_mips_top/inst_biu/inst_icache/ram_read_en + RAMB16_X3Y6.CLKB Trcck_ENB 0.518 inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 + inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 ------------------------------------------------- --------------------------- - Total 8.137ns (1.719ns logic, 6.418ns route) - (21.1% logic, 78.9% route) + Total 9.556ns (4.556ns logic, 5.000ns route) + (47.7% logic, 52.3% route) -------------------------------------------------------------------------------- -Delay: 8.117ns (data path) - Source: arb_gnt_0 (FF) - Destination: inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM64.SLICEM_F (RAM) - Data Path Delay: 8.117ns (Levels of Logic = 7) - Source Clock: CLK_O rising at 0.000ns +Slack: 0.010ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 (FF) + Destination: inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 (RAM) + Requirement: 9.900ns + Data Path Delay: 9.556ns (Levels of Logic = 23) + Clock Path Skew: -0.274ns (2.666 - 2.940) + Source Clock: cpu_clk rising at 0.000ns + Destination Clock: cpu_clk rising at 9.900ns + Clock Uncertainty: 0.060ns - Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM64.SLICEM_F + Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.120ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 to inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X36Y67.XQ Tcko 0.360 arb_gnt<0> - arb_gnt_0 - SLICE_X34Y65.G1 net (fanout=114) 1.226 arb_gnt<0> - SLICE_X34Y65.Y Tilo 0.195 inst_flash_port/ADDR_I_r<16> - Mmux_ADDR_O251 - SLICE_X34Y69.F4 net (fanout=6) 0.361 ADDR_O<31> - SLICE_X34Y69.X Tilo 0.195 N382 - CYC_I_flash_SW0 - SLICE_X39Y66.G4 net (fanout=2) 0.538 N382 - SLICE_X39Y66.Y Tilo 0.194 N102 - CYC_I_flash - SLICE_X39Y65.F2 net (fanout=39) 0.538 CYC_I_flash - SLICE_X39Y65.X Tilo 0.194 SRDY_I26 - SRDY_I26 - SLICE_X35Y51.G4 net (fanout=1) 0.581 SRDY_I26 - SLICE_X35Y51.Y Tilo 0.194 ADDR_O_cpu<31> - SRDY_I36 - SLICE_X35Y50.F1 net (fanout=7) 0.418 SRDY_I - SLICE_X35Y50.X Tilo 0.194 ADDR_O_cpu<16> - SRDY_I_cpu - SLICE_X33Y48.F1 net (fanout=1) 0.799 SRDY_I_cpu - SLICE_X33Y48.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> - inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 - SLICE_X30Y34.F1 net (fanout=67) 1.936 inst_mips_top/inst_biu/inst_bout_fifo/ptr_r<0> + SLICE_X17Y13.YQ Tcko 0.340 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 + inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 + SLICE_X16Y11.F2 net (fanout=12) 0.783 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 + SLICE_X16Y11.COUT Topcyf 0.576 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X16Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X16Y12.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X16Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X16Y13.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X16Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X16Y14.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<6> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X16Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X16Y15.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X16Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X16Y16.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<0> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X16Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X16Y17.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<6> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X16Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X16Y18.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<3> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X16Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X16Y19.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X16Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X16Y20.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<9> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X16Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X16Y21.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X16Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X16Y22.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X16Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X16Y23.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X16Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X16Y24.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X16Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X16Y25.COUT Tbyp 0.089 inst_mips_top/inst_biu/inst_dcache/tag_reg<5> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X16Y26.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X16Y26.YMUX Tciny 0.513 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> + SLICE_X13Y30.F4 net (fanout=4) 0.917 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> + SLICE_X13Y30.X Tilo 0.194 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_ovf + inst_mips_top/inst_pipeline/EX_events_alu_alu_ovf + SLICE_X13Y32.G3 net (fanout=1) 0.423 inst_mips_top/inst_pipeline/EX_events_alu_alu_ovf + SLICE_X13Y32.Y Tilo 0.194 inst_mips_top/RST_I_shift3 + inst_mips_top/inst_pipeline/EX_stage_exc23 + SLICE_X13Y32.F3 net (fanout=17) 0.245 inst_mips_top/inst_pipeline/EX_stage_exc + SLICE_X13Y32.X Tilo 0.194 inst_mips_top/RST_I_shift3 + inst_mips_top/inst_pipeline/sdu_ID_nop + SLICE_X14Y34.G4 net (fanout=15) 0.405 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + SLICE_X14Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 + inst_mips_top/inst_cop/cop_pipe_ID_RFE31 + SLICE_X14Y34.F4 net (fanout=6) 0.169 inst_mips_top/inst_cop/cop_pipe_ID_RFE + SLICE_X14Y34.X Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 + inst_mips_top/inst_cop/ctrl_out_exc_commit11 + SLICE_X16Y34.G2 net (fanout=1) 0.583 inst_mips_top/inst_cop/exc_state_FSM_FFd3-In + SLICE_X16Y34.Y Tilo 0.195 inst_mips_top/inst_biu/inst_icache/cache_req + inst_mips_top/inst_pipeline/imem_en47 + SLICE_X16Y34.F4 net (fanout=2) 0.164 inst_mips_top/imem_en + SLICE_X16Y34.X Tilo 0.195 inst_mips_top/inst_biu/inst_icache/cache_req + inst_mips_top/inst_biu/inst_icache/ram_read_en1 + RAMB16_X3Y6.ENB net (fanout=18) 1.312 inst_mips_top/inst_biu/inst_icache/ram_read_en + RAMB16_X3Y6.CLKB Trcck_ENB 0.518 inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 + inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 ------------------------------------------------- --------------------------- - Total 8.117ns (1.720ns logic, 6.397ns route) - (21.2% logic, 78.8% route) + Total 9.556ns (4.555ns logic, 5.001ns route) + (47.7% logic, 52.3% route) -------------------------------------------------------------------------------- @@ -1262,13 +1087,13 @@ Timing constraint: TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 ns HIGH 50%; 787 paths analyzed, 73 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 5.205ns. + Minimum period is 6.102ns. -------------------------------------------------------------------------------- -Slack: 74.795ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) - Destination: inst_ac97_wb/inst_ac_io/cnt_1 (FF) +Slack: 73.898ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_1 (FF) + Destination: inst_ac97_wb/inst_ac_io/cnt_9 (FF) Requirement: 80.000ns - Data Path Delay: 5.096ns (Levels of Logic = 4) + Data Path Delay: 5.993ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 80.000ns @@ -1280,37 +1105,37 @@ Slack: 74.795ns (requirement - (data path - clock path skew + u Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_1 + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_1 to inst_ac97_wb/inst_ac_io/cnt_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X54Y12.XQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> - inst_ac97_wb/inst_ac_io/cnt_0 - SLICE_X55Y15.G4 net (fanout=9) 1.142 inst_ac97_wb/inst_ac_io/cnt<0> - SLICE_X55Y15.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 - inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 - SLICE_X55Y15.F4 net (fanout=1) 0.159 N963 - SLICE_X55Y15.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 - inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 - SLICE_X55Y17.G4 net (fanout=3) 0.358 inst_ac97_wb/inst_ac_io/N9 - SLICE_X55Y17.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_2 - inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 - SLICE_X53Y25.G4 net (fanout=10) 0.828 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 - SLICE_X53Y25.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 - inst_ac97_wb/inst_ac_io/cnt_not00021 - SLICE_X54Y12.CE net (fanout=5) 0.919 inst_ac97_wb/inst_ac_io/cnt_not0002 - SLICE_X54Y12.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<0> + SLICE_X56Y22.YQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> inst_ac97_wb/inst_ac_io/cnt_1 + SLICE_X56Y27.G1 net (fanout=8) 0.877 inst_ac97_wb/inst_ac_io/cnt<1> + SLICE_X56Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 + SLICE_X56Y27.F3 net (fanout=1) 0.213 N966 + SLICE_X56Y27.X Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 + SLICE_X54Y24.G1 net (fanout=3) 0.825 inst_ac97_wb/inst_ac_io/N9 + SLICE_X54Y24.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> + inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 + SLICE_X50Y34.G3 net (fanout=10) 1.102 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X50Y34.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_in/bitcnt<0> + inst_ac97_wb/inst_ac_io/cnt_not00021 + SLICE_X56Y26.CE net (fanout=5) 1.282 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X56Y26.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<8> + inst_ac97_wb/inst_ac_io/cnt_9 ------------------------------------------------- --------------------------- - Total 5.096ns (1.690ns logic, 3.406ns route) - (33.2% logic, 66.8% route) + Total 5.993ns (1.694ns logic, 4.299ns route) + (28.3% logic, 71.7% route) -------------------------------------------------------------------------------- -Slack: 74.795ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) - Destination: inst_ac97_wb/inst_ac_io/cnt_3 (FF) +Slack: 73.898ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_1 (FF) + Destination: inst_ac97_wb/inst_ac_io/cnt_8 (FF) Requirement: 80.000ns - Data Path Delay: 5.096ns (Levels of Logic = 4) + Data Path Delay: 5.993ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 80.000ns @@ -1322,37 +1147,37 @@ Slack: 74.795ns (requirement - (data path - clock path skew + u Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_3 + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_1 to inst_ac97_wb/inst_ac_io/cnt_8 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X54Y12.XQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> - inst_ac97_wb/inst_ac_io/cnt_0 - SLICE_X55Y15.G4 net (fanout=9) 1.142 inst_ac97_wb/inst_ac_io/cnt<0> - SLICE_X55Y15.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X56Y22.YQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> + inst_ac97_wb/inst_ac_io/cnt_1 + SLICE_X56Y27.G1 net (fanout=8) 0.877 inst_ac97_wb/inst_ac_io/cnt<1> + SLICE_X56Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 - SLICE_X55Y15.F4 net (fanout=1) 0.159 N963 - SLICE_X55Y15.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X56Y27.F3 net (fanout=1) 0.213 N966 + SLICE_X56Y27.X Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 - SLICE_X55Y17.G4 net (fanout=3) 0.358 inst_ac97_wb/inst_ac_io/N9 - SLICE_X55Y17.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_2 + SLICE_X54Y24.G1 net (fanout=3) 0.825 inst_ac97_wb/inst_ac_io/N9 + SLICE_X54Y24.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 - SLICE_X53Y25.G4 net (fanout=10) 0.828 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 - SLICE_X53Y25.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X50Y34.G3 net (fanout=10) 1.102 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X50Y34.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_in/bitcnt<0> inst_ac97_wb/inst_ac_io/cnt_not00021 - SLICE_X54Y13.CE net (fanout=5) 0.919 inst_ac97_wb/inst_ac_io/cnt_not0002 - SLICE_X54Y13.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<2> - inst_ac97_wb/inst_ac_io/cnt_3 + SLICE_X56Y26.CE net (fanout=5) 1.282 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X56Y26.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<8> + inst_ac97_wb/inst_ac_io/cnt_8 ------------------------------------------------- --------------------------- - Total 5.096ns (1.690ns logic, 3.406ns route) - (33.2% logic, 66.8% route) + Total 5.993ns (1.694ns logic, 4.299ns route) + (28.3% logic, 71.7% route) -------------------------------------------------------------------------------- -Slack: 74.795ns (requirement - (data path - clock path skew + uncertainty)) +Slack: 74.014ns (requirement - (data path - clock path skew + uncertainty)) Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) - Destination: inst_ac97_wb/inst_ac_io/cnt_2 (FF) + Destination: inst_ac97_wb/inst_ac_io/cnt_9 (FF) Requirement: 80.000ns - Data Path Delay: 5.096ns (Levels of Logic = 4) + Data Path Delay: 5.877ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 80.000ns @@ -1364,35 +1189,35 @@ Slack: 74.795ns (requirement - (data path - clock path skew + u Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_2 + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X54Y12.XQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> + SLICE_X56Y22.XQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> inst_ac97_wb/inst_ac_io/cnt_0 - SLICE_X55Y15.G4 net (fanout=9) 1.142 inst_ac97_wb/inst_ac_io/cnt<0> - SLICE_X55Y15.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X56Y27.G2 net (fanout=9) 0.761 inst_ac97_wb/inst_ac_io/cnt<0> + SLICE_X56Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 - SLICE_X55Y15.F4 net (fanout=1) 0.159 N963 - SLICE_X55Y15.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X56Y27.F3 net (fanout=1) 0.213 N966 + SLICE_X56Y27.X Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 - SLICE_X55Y17.G4 net (fanout=3) 0.358 inst_ac97_wb/inst_ac_io/N9 - SLICE_X55Y17.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_2 + SLICE_X54Y24.G1 net (fanout=3) 0.825 inst_ac97_wb/inst_ac_io/N9 + SLICE_X54Y24.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 - SLICE_X53Y25.G4 net (fanout=10) 0.828 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 - SLICE_X53Y25.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X50Y34.G3 net (fanout=10) 1.102 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X50Y34.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_in/bitcnt<0> inst_ac97_wb/inst_ac_io/cnt_not00021 - SLICE_X54Y13.CE net (fanout=5) 0.919 inst_ac97_wb/inst_ac_io/cnt_not0002 - SLICE_X54Y13.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<2> - inst_ac97_wb/inst_ac_io/cnt_2 + SLICE_X56Y26.CE net (fanout=5) 1.282 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X56Y26.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<8> + inst_ac97_wb/inst_ac_io/cnt_9 ------------------------------------------------- --------------------------- - Total 5.096ns (1.690ns logic, 3.406ns route) - (33.2% logic, 66.8% route) + Total 5.877ns (1.694ns logic, 4.183ns route) + (28.8% logic, 71.2% route) -------------------------------------------------------------------------------- -1 constraint not met. +All constraints were met. Data Sheet report: @@ -1404,7 +1229,7 @@ Clock to Setup on destination clock sys_ac97_bit_clk | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ----------------+---------+---------+---------+---------+ -sys_ac97_bit_clk| 6.860| 3.451| | 2.366| +sys_ac97_bit_clk| 9.594| 4.206| | 2.132| ----------------+---------+---------+---------+---------+ Clock to Setup on destination clock sys_clk_in @@ -1412,25 +1237,25 @@ Clock to Setup on destination clock sys_clk_in | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ -sys_clk_in | 10.018| 4.756| 4.893| 3.181| +sys_clk_in | 9.899| 4.847| 4.836| 2.953| ---------------+---------+---------+---------+---------+ Timing summary: --------------- -Timing errors: 5 Score: 483 +Timing errors: 0 Score: 0 -Constraints cover 1399013 paths, 0 nets, and 42608 connections +Constraints cover 1334502 paths, 0 nets, and 42622 connections Design statistics: - Minimum period: 10.018ns{1} (Maximum frequency: 99.820MHz) + Minimum period: 9.899ns{1} (Maximum frequency: 101.020MHz) ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. -Analysis completed Sun Feb 07 21:04:11 2010 +Analysis completed Tue Feb 09 13:08:32 2010 -------------------------------------------------------------------------------- Trace Settings: diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp index 70035dd..43ab881 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp +++ b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp @@ -10,28 +10,27 @@ Target Device : xc4vsx35 Target Package : ff668 Target Speed : -10 Stepping Level : ES -Mapper Version : virtex4 -- $Revision: 1.2 $ -Mapped Date : Sun Feb 07 20:50:10 2010 +Mapper Version : virtex4 -- $Revision: 1.3 $ +Mapped Date : Tue Feb 09 12:50:04 2010 Design Summary -------------- Number of errors: 0 Number of warnings: 69 Logic Utilization: - Number of Slice Flip Flops: 5,368 out of 30,720 17% - Number of 4 input LUTs: 8,515 out of 30,720 27% + Number of Slice Flip Flops: 5,374 out of 30,720 17% + Number of 4 input LUTs: 8,573 out of 30,720 27% Logic Distribution: - Number of occupied Slices: 5,888 out of 15,360 38% - Number of Slices containing only related logic: 5,888 out of 5,888 100% - Number of Slices containing unrelated logic: 0 out of 5,888 0% + Number of occupied Slices: 6,053 out of 15,360 39% + Number of Slices containing only related logic: 6,053 out of 6,053 100% + Number of Slices containing unrelated logic: 0 out of 6,053 0% *See NOTES below for an explanation of the effects of unrelated logic. - Total Number of 4 input LUTs: 8,913 out of 30,720 29% - Number used as logic: 7,515 + Total Number of 4 input LUTs: 8,971 out of 30,720 29% + Number used as logic: 7,573 Number used as a route-thru: 398 - Number used as 16x1 RAMs: 6 Number used for Dual Port RAMs: 792 (Two LUTs used per Dual Port RAM) - Number used as Shift registers: 202 + Number used as Shift registers: 208 Number of bonded IOBs: 226 out of 448 50% IOB Flip Flops: 350 IOB Dual-Data Rate Flops: 42 @@ -42,9 +41,9 @@ Logic Distribution: Number of DCM_ADVs: 4 out of 8 50% Number of BSCAN_VIRTEX4s: 1 out of 4 25% -Peak Memory Usage: 510 MB -Total REAL time to MAP completion: 8 mins 4 secs -Total CPU time to MAP completion: 7 mins 57 secs +Peak Memory Usage: 512 MB +Total REAL time to MAP completion: 8 mins 30 secs +Total CPU time to MAP completion: 8 mins 17 secs Table of Contents ----------------- @@ -1501,17 +1500,16 @@ Area Group "AG_inst_mips_top" RAMB16_X0Y0:RAMB16_X0Y6,RAMB16_X1Y0:RAMB16_X1Y6,RAMB16_X2Y0:RAMB16_X2Y6,RAMB16_X 3Y0:RAMB16_X3Y6 Area Group Logic Utilization: - Number of Slice Flip Flops: 1,915 out of 4,320 44% + Number of Slice Flip Flops: 1,922 out of 4,320 44% Logic Distribution: - Number of occupied Slices: 2,148 out of 2,160 99% - Number of Slices containing only related logic: 2,148 out of 2,148 100% - Total Number of 4 input LUTs: 4,220 out of 4,320 97% - Number used as logic: 3,551 + Number of occupied Slices: 2,124 out of 2,160 98% + Number of Slices containing only related logic: 2,124 out of 2,124 100% + Total Number of 4 input LUTs: 4,218 out of 4,320 97% + Number used as logic: 3,549 Number used as route-thru: 58 - Number used as 16x1 RAMs: 2 Number used as Dual Port RAMs: 586 (Two LUTs used per Dual Port RAM) - Number used as Shift registers: 23 + Number used as Shift registers: 25 Number of Block RAMs: 27 out of 28 96% @@ -1544,34 +1542,34 @@ Section 14 - Utilization by Hierarchy +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48 | BUFG | BUFIO | BUFR | DCM | Full Hierarchical Name | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| mips_sys/ | | 1399/8096 | 28/5368 | 848/8913 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys | -| +inst_ac97_wb | | 183/793 | 118/671 | 186/616 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb | -| ++inst_ac_io | | 22/579 | 13/524 | 29/377 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io | -| +++inst_ac_in | | 269/275 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in | -| ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 | +| mips_sys/ | | 1416/8338 | 28/5374 | 891/8971 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys | +| +inst_ac97_wb | | 181/838 | 118/671 | 185/617 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb | +| ++inst_ac_io | | 21/623 | 13/524 | 29/378 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io | +| +++inst_ac_in | | 285/290 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in | +| ++++singleshot_inst1 | | 2/2 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 | | ++++singleshot_inst2 | | 3/3 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 | -| +++inst_ac_out | | 279/282 | 247/249 | 243/245 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out | +| +++inst_ac_out | | 309/312 | 247/249 | 244/246 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out | | ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1 | -| ++inst_tx_fifo | | 1/31 | 0/29 | 1/53 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo | +| ++inst_tx_fifo | | 1/34 | 0/29 | 1/54 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo | | +++inst_dpram_1w1r | | 1/1 | 0/0 | 1/1 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 29/29 | 29/29 | 51/51 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl | -| +inst_clockgen | | 51/57 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen | +| +++inst_fifo_sync_ctrl | | 32/32 | 29/29 | 52/52 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl | +| +inst_clockgen | | 41/47 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen | | ++Mshreg_reset_pipe0_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_0 | | ++Mshreg_reset_pipe0_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_1 | | ++Mshreg_reset_pipe1_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_0 | | ++Mshreg_reset_pipe1_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_1 | | ++Mshreg_reset_pipe2_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_0 | | ++Mshreg_reset_pipe2_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_1 | -| +inst_flash_port | | 79/79 | 64/64 | 49/49 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port | -| +inst_gpio_wb | | 267/267 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb | -| +inst_mips_top | | 20/2827 | 22/1916 | 13/4118 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top | +| +inst_flash_port | | 81/81 | 65/65 | 54/54 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port | +| +inst_gpio_wb | | 299/299 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb | +| +inst_mips_top | | 25/2831 | 22/1920 | 13/4123 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top | | ++Mshreg_reset_delay_15 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_15 | | ++Mshreg_reset_delay_19 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_19 | | ++Mshreg_reset_delay_30 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_30 | -| ++inst_biu | | 188/802 | 97/536 | 208/911 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu | -| +++inst_bin_fifo | | 4/102 | 0/62 | 4/107 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo | -| ++++inst_dpram_1w1r | | 57/57 | 32/32 | 64/64 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 13/41 | 12/30 | 5/39 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl | +| ++inst_biu | | 193/811 | 97/534 | 209/915 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu | +| +++inst_bin_fifo | | 4/96 | 0/62 | 4/107 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo | +| ++++inst_dpram_1w1r | | 53/53 | 32/32 | 64/64 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r | +| ++++inst_fifo_async_ctrl | | 12/39 | 12/30 | 5/39 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl | | +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1583,10 +1581,10 @@ Section 14 - Utilization by Hierarchy | +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | | +++++inst_gray_counter_r | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| +++++inst_gray_counter_w | | 10/10 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_bout_fifo | | 3/146 | 0/99 | 3/176 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo | -| ++++inst_dpram_1w1r | | 101/101 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 13/42 | 14/32 | 5/39 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl | +| +++++inst_gray_counter_w | | 9/9 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +++inst_bout_fifo | | 4/148 | 0/97 | 4/178 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo | +| ++++inst_dpram_1w1r | | 103/103 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r | +| ++++inst_fifo_async_ctrl | | 12/41 | 12/30 | 5/40 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl | | +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1597,46 +1595,46 @@ Section 14 - Utilization by Hierarchy | +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | | +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| +++++inst_gray_counter_r | | 8/8 | 9/9 | 11/11 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| +++++inst_gray_counter_r | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | | +++++inst_gray_counter_w | | 11/11 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_dcache | | 167/167 | 120/120 | 148/148 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache | +| +++inst_dcache | | 180/180 | 120/120 | 148/148 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache | | ++++gen_data_ram[0].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[0].inst_data_ram | | ++++gen_data_ram[1].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[1].inst_data_ram | | ++++gen_data_ram[2].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram | | ++++gen_data_ram[3].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[3].inst_data_ram | | ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/inst_tag_ram | -| +++inst_icache | | 118/118 | 81/81 | 120/120 | 0/0 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache | +| +++inst_icache | | 113/113 | 81/81 | 121/121 | 0/0 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache | | ++++inst_data_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_data_ram | | ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_tag_ram | | +++inst_write_fifo | | 1/81 | 0/77 | 1/152 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo | | ++++inst_dpram_1w1r | | 67/67 | 66/66 | 133/133 | 132/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_dpram_1w1r | | ++++inst_fifo_sync_ctrl | | 13/13 | 11/11 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl | | ++inst_cop | | 214/214 | 190/190 | 239/239 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop | -| ++inst_pipeline | | 875/1788 | 641/1168 | 1296/2952 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline | +| ++inst_pipeline | | 854/1778 | 646/1174 | 1297/2953 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline | | +++inst_alu | | 63/63 | 1/1 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu | | +++inst_bcu | | 8/8 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_bcu | -| +++inst_muldiv | | 555/555 | 526/526 | 1025/1025 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv | +| +++inst_muldiv | | 563/563 | 526/526 | 1025/1025 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv | | +++inst_reg_dual | | 128/128 | 0/0 | 256/256 | 256/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_reg_dual | -| +++inst_shifter | | 159/159 | 0/0 | 240/240 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter | -| +inst_ps2_phy_0 | | 0/13 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 | +| +++inst_shifter | | 162/162 | 1/1 | 240/240 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter | +| +inst_ps2_phy_0 | | 0/12 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 | | ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_clk | -| ++Inst_debounce_data | | 7/7 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_data | -| +inst_ps2_phy_1 | | 0/11 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1 | -| ++Inst_debounce_clk | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk | -| ++Inst_debounce_data | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data | -| +inst_ps2_wb_0 | | 33/157 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 | -| ++inst_ps2_core | | 124/124 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core | -| +inst_ps2_wb_1 | | 30/146 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 | -| ++inst_ps2_core | | 116/116 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core | -| +inst_rom_wb | | 1/72 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb | -| ++inst_rom | | 71/71 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom | -| +inst_sdram_ctrl_frontend_wb | | 97/649 | 0/455 | 145/599 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb | +| ++Inst_debounce_data | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_data | +| +inst_ps2_phy_1 | | 0/13 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1 | +| ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk | +| ++Inst_debounce_data | | 7/7 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data | +| +inst_ps2_wb_0 | | 36/158 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 | +| ++inst_ps2_core | | 122/122 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core | +| +inst_ps2_wb_1 | | 32/151 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 | +| ++inst_ps2_core | | 119/119 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core | +| +inst_rom_wb | | 1/73 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb | +| ++inst_rom | | 72/72 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom | +| +inst_sdram_ctrl_frontend_wb | | 109/676 | 0/455 | 145/598 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb | | ++inst_cat_fifo | | 1/16 | 0/13 | 1/24 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo | | +++inst_dpram_1w1r | | 1/1 | 0/0 | 1/1 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r | | +++inst_fifo_sync_ctrl | | 14/14 | 13/13 | 22/22 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl | -| ++inst_read_fifo | | 5/56 | 0/36 | 6/55 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo | +| ++inst_read_fifo | | 5/57 | 0/36 | 6/55 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 18/51 | 14/36 | 7/49 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl | +| +++inst_fifo_async_ctrl | | 18/52 | 14/36 | 7/49 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl | | ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1649,14 +1647,14 @@ Section 14 - Utilization by Hierarchy | ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | | ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | -| ++++inst_gray_counter_r | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| ++++inst_gray_counter_r | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | | ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| ++inst_sdram_ctrl | | 0/424 | 0/370 | 0/320 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl | +| ++inst_sdram_ctrl | | 0/436 | 0/370 | 0/319 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl | | +++inst_ddr_phy | | 171/172 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy | | ++++Mshreg_u_tag_pipe_4_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/Mshreg_u_tag_pipe_4_0 | -| +++inst_sd_cmd_fifo | | 3/65 | 0/41 | 4/60 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo | +| +++inst_sd_cmd_fifo | | 3/67 | 0/41 | 4/60 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo | | ++++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 23/62 | 17/41 | 11/56 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl | +| ++++inst_fifo_async_ctrl | | 23/64 | 17/41 | 11/56 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl | | +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | +++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | @@ -1672,12 +1670,12 @@ Section 14 - Utilization by Hierarchy | +++++Mshreg_p2_2_BRB1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_2_BRB1 | | +++++Mshreg_p2_2_BRB2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_2_BRB2 | | +++++inst_gray_counter_r | | 15/15 | 13/13 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| +++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_sdram_cmd | | 47/47 | 13/13 | 66/66 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd | -| +++inst_sdram_ctrl | | 140/140 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl | -| ++inst_write_fifo | | 5/56 | 0/36 | 6/55 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo | +| +++++inst_gray_counter_w | | 12/12 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +++inst_sdram_cmd | | 46/46 | 13/13 | 65/65 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd | +| +++inst_sdram_ctrl | | 151/151 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl | +| ++inst_write_fifo | | 5/58 | 0/36 | 6/55 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 18/51 | 14/36 | 7/49 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl | +| +++inst_fifo_async_ctrl | | 18/53 | 14/36 | 7/49 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl | | ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1690,31 +1688,31 @@ Section 14 - Utilization by Hierarchy | ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | | ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | -| ++++inst_gray_counter_r | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| ++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +inst_uart_wb_0 | | 58/103 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 | -| ++inst_uart_rx | | 0/28 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx | +| ++++inst_gray_counter_r | | 12/12 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +inst_uart_wb_0 | | 59/104 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 | +| ++inst_uart_rx | | 0/27 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/buf | -| +++kcuart | | 20/20 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart | -| ++inst_uart_tx | | 0/17 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx | +| +++kcuart | | 19/19 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart | +| ++inst_uart_tx | | 0/18 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/buf | -| +++kcuart | | 9/9 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart | -| +inst_uart_wb_1 | | 56/105 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 | -| ++inst_uart_rx | | 0/30 | 0/29 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx | +| +++kcuart | | 10/10 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart | +| +inst_uart_wb_1 | | 61/107 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 | +| ++inst_uart_rx | | 0/28 | 0/29 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/buf | -| +++kcuart | | 22/22 | 24/24 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/kcuart | -| ++inst_uart_tx | | 0/19 | 0/15 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx | +| +++kcuart | | 20/20 | 24/24 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/kcuart | +| ++inst_uart_tx | | 0/18 | 0/15 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/buf | -| +++kcuart | | 11/11 | 10/10 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart | -| +inst_usb_port | | 30/30 | 26/26 | 26/26 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port | -| +inst_vga_frontend | | 783/1388 | 793/1245 | 766/1554 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend | +| +++kcuart | | 10/10 | 10/10 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart | +| +inst_usb_port | | 37/37 | 27/27 | 31/31 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port | +| +inst_vga_frontend | | 868/1495 | 793/1245 | 766/1554 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend | | ++inst_blitfifo | | 1/25 | 0/21 | 1/40 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_dpram_1w1r | | +++inst_fifo_sync_ctrl | | 24/24 | 21/21 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl | -| ++inst_bus_fifo | | 1/114 | 0/110 | 1/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo | +| ++inst_bus_fifo | | 2/115 | 0/110 | 2/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo | | +++inst_dpram_1w1r | | 104/104 | 103/103 | 207/207 | 206/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 9/9 | 7/7 | 11/11 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl | -| ++inst_char_gen | | 180/192 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen | +| +++inst_fifo_sync_ctrl | | 9/9 | 7/7 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl | +| ++inst_char_gen | | 196/208 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen | | +++Mshreg_csr_posx_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_0 | | +++Mshreg_csr_posx_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_1 | | +++Mshreg_csr_posx_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_2 | @@ -1729,9 +1727,9 @@ Section 14 - Utilization by Hierarchy | +++Mshreg_csr_posy_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_4 | | +++inst_ascii_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_ascii_ram | | +++inst_char_rom | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_char_rom | -| ++inst_linefifo | | 1/172 | 0/145 | 1/179 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo | +| ++inst_linefifo | | 1/173 | 0/145 | 1/179 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 85/171 | 87/145 | 84/178 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl | +| +++inst_fifo_async_ctrl | | 83/172 | 87/145 | 84/178 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl | | ++++Mshreg_bcnt2_ar_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_0 | | ++++Mshreg_bcnt2_ar_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_1 | | ++++Mshreg_bcnt2_ar_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_10 | @@ -1778,12 +1776,12 @@ Section 14 - Utilization by Hierarchy | ++++Mshreg_gcnt2_w_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_7 | | ++++Mshreg_gcnt2_w_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_8 | | ++++Mshreg_gcnt2_w_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_9 | -| ++++inst_gray_counter_r | | 20/20 | 23/23 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| ++++inst_gray_counter_w | | 20/20 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| ++inst_vga_backend | | 60/102 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend | -| +++inst_vga_timing | | 0/42 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing | +| ++++inst_gray_counter_r | | 22/22 | 23/23 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| ++++inst_gray_counter_w | | 21/21 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| ++inst_vga_backend | | 65/106 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend | +| +++inst_vga_timing | | 0/41 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing | | ++++inst_vga_sync_h | | 21/21 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h | -| ++++inst_vga_sync_v | | 21/21 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v | +| ++++inst_vga_sync_v | | 20/20 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slices can be packed with basic elements from multiple hierarchies.