jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- redesigned :

Browse Source 
- added data input register
  - PISOs can be cascaded


Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@817 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-25 09:33:02 +00:00
parent 2978ddd09a
commit 80f57311e4
1 changed files with 71 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/emac/src/piso.vhd
+71 -55
View File
@@ -20,7 +20,8 @@ ENTITY piso IS
din_rdy : out STD_LOGIC; din_rdy : out STD_LOGIC;
din_be : in unsigned(data_width_in/data_width_out-1 downto 0); din_be : in unsigned(data_width_in/data_width_out-1 downto 0);
din : in unsigned(data_width_in-1 downto 0); din : in unsigned(data_width_in-1 downto 0);
dout_en : out STD_LOGIC; dout_vld : out STD_LOGIC;
dout_en : in STD_LOGIC;
dout : out unsigned(data_width_out-1 downto 0) dout : out unsigned(data_width_out-1 downto 0)
); );
@@ -31,72 +32,67 @@ ARCHITECTURE behavior OF piso IS
constant num_shifts : natural := data_width_in/data_width_out; constant num_shifts : natural := data_width_in/data_width_out;
signal pre_fin : STD_LOGIC; signal pre_fin : STD_LOGIC;
signal rdy : STD_LOGIC; signal rdy : STD_LOGIC;
signal shift_cnt_pipe : unsigned(num_shifts-2 downto 0); signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0);
signal shift_pipe : unsigned(data_width_in-1 downto 0); signal shift_pipe : unsigned(data_width_in-1 downto 0);
signal vld_pipe : unsigned(num_shifts-1 downto 0); signal vld_pipe : unsigned(num_shifts-1 downto 0);
signal din_reg : unsigned(data_width_in-1 downto 0);
signal din_be_reg : unsigned(num_shifts-1 downto 0);
signal din_vld_reg : STD_LOGIC;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
begin begin
pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1); pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1);
din_rdy <= rdy; din_rdy <= rdy;
dout_vld <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
else shift_pipe(data_width_out-1 downto 0); else shift_pipe(data_width_out-1 downto 0);
dout_en <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
-------------------------------------------------------------------------- --------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
rdy <= '0';
elsif pre_fin = '1' and rdy = '0' then
rdy <= '1';
elsif din_vld = '1' then
rdy <= not din_vld_reg;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
din_vld_reg <= '0';
elsif pre_fin = '1' and dout_en = '1' then
din_vld_reg <= din_vld;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if din_vld = '1' and rdy = '1' then
din_reg <= din;
din_be_reg <= din_be;
end if;
end if;
end process;
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
shift_cnt_pipe <= (others => '1'); shift_cnt_pipe <= (others => '1');
elsif rdy = '1' then elsif dout_en = '1' then
if din_vld = '1' then if pre_fin = '1' and din_vld_reg = '1' then
shift_cnt_pipe <= (others => '0'); shift_cnt_pipe <= (others => '0');
end if;
else
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1';
end if;
end if;
end process;
--------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if rdy = '1' then
if din_vld = '1' then
shift_pipe <= din;
end if;
else
if (msb_first) then
shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
else else
shift_pipe <= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out); shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
vld_pipe <= (others => '0');
elsif rdy = '1' then
vld_pipe <= (others => '0');
if din_vld = '1' then
vld_pipe <= din_be;
end if;
else
if (msb_first) then
vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0';
else
vld_pipe <= '0' & vld_pipe(vld_pipe'left downto 1);
end if; end if;
end if; end if;
end if; end if;
@@ -106,16 +102,36 @@ end process;
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if dout_en = '1' then
if pre_fin = '1' and din_vld_reg = '1' then
shift_pipe <= din_reg;
else
if (msb_first) then
shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
else
shift_pipe <= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
rdy <= '0'; vld_pipe <= (others => '0');
elsif rdy = '1' then elsif dout_en = '1' then
if pre_fin = '1' then if pre_fin = '1' and din_vld_reg = '1' then
if din_vld = '1' then vld_pipe <= din_be_reg;
rdy <= '0'; else
if (msb_first) then
vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0';
else
vld_pipe <= '0' & vld_pipe(vld_pipe'left downto 1);
end if; end if;
end if; end if;
elsif pre_fin = '1' then
rdy <= '1';
end if; end if;
end if; end if;
end process; end process;