From 80f57311e4b970807cffddbf01391c0516a93209 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Thu, 25 Mar 2010 09:33:02 +0000
Subject: [PATCH] - redesigned :   - added data input register   - PISOs can be
 cascaded

Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@817 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/emac/src/piso.vhd | 126 ++++++++++++++++++++++++------------------
 1 file changed, 71 insertions(+), 55 deletions(-)

diff --git a/lib/emac/src/piso.vhd b/lib/emac/src/piso.vhd
index 6797125..e8c4a4b 100644
--- a/lib/emac/src/piso.vhd
+++ b/lib/emac/src/piso.vhd
@@ -20,7 +20,8 @@ ENTITY piso IS
 		din_rdy		: out STD_LOGIC;
 		din_be		: in  unsigned(data_width_in/data_width_out-1 downto 0);
 		din			: in  unsigned(data_width_in-1 downto 0);
-		dout_en		: out STD_LOGIC;
+		dout_vld	: out STD_LOGIC;
+		dout_en		: in  STD_LOGIC;
 		dout		: out unsigned(data_width_out-1 downto 0)
 		
 	);
@@ -31,72 +32,67 @@ ARCHITECTURE behavior OF piso IS
 	constant num_shifts		: natural := data_width_in/data_width_out;
 	signal pre_fin			: STD_LOGIC;
 	signal rdy				: STD_LOGIC;
-	signal shift_cnt_pipe	: unsigned(num_shifts-2 downto 0);
+	signal shift_cnt_pipe	: unsigned(num_shifts-1 downto 0);
 	signal shift_pipe		: unsigned(data_width_in-1 downto 0);
 	signal vld_pipe			: unsigned(num_shifts-1 downto 0);
+	signal din_reg			: unsigned(data_width_in-1 downto 0);
+	signal din_be_reg		: unsigned(num_shifts-1 downto 0);
+	signal din_vld_reg		: STD_LOGIC;
 	
 --------------------------------------------------------------------------
 begin
 
 	pre_fin		<= shift_cnt_pipe(shift_cnt_pipe'left-1);
-
 	din_rdy		<= rdy;
+	dout_vld	<= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
 	dout		<= 		shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
 				else	shift_pipe(data_width_out-1 downto 0);
 
-	dout_en		<= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
-	
 --------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			rdy			<= '0';
+		elsif pre_fin = '1' and rdy = '0' then
+			rdy		<= '1';
+		elsif din_vld = '1' then
+			rdy			<= not din_vld_reg;
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			din_vld_reg	<= '0';
+		elsif pre_fin = '1' and dout_en = '1' then
+			din_vld_reg	<= din_vld;
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if din_vld = '1' and rdy = '1' then
+			din_reg		<= din;
+			din_be_reg	<= din_be;
+		end if;
+	end if;
+end process;
+
 process(clk)
 begin
 	if rising_edge(clk) then
 		if rst = '1' then
 			shift_cnt_pipe	<= (others => '1');
-		elsif rdy = '1' then
-			if din_vld = '1' then
+		elsif dout_en = '1' then
+			if pre_fin = '1' and din_vld_reg = '1' then
 				shift_cnt_pipe	<= (others => '0');
-			end if;
-		else
-			shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
-		end if;
-	end if;
-end process;
-
---------------------------------------------------------------------------
-process(clk)
-begin
-	if rising_edge(clk) then
-		if rdy = '1' then
-			if din_vld = '1' then
-				shift_pipe		<= din;
-			end if;
-		else
-			if (msb_first) then
-				shift_pipe		<= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
 			else
-				shift_pipe		<= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
-			end if;
-			
-		end if;
-	end if;
-end process;
-
---------------------------------------------------------------------------
-process(clk)
-begin
-	if rising_edge(clk) then
-		if rst = '1' then
-			vld_pipe	<= (others => '0');
-		elsif rdy = '1' then
-			vld_pipe	<= (others => '0');
-			if din_vld = '1' then
-				vld_pipe		<= din_be;
-			end if;
-		else
-			if (msb_first) then
-				vld_pipe		<= vld_pipe(vld_pipe'left-1 downto 0) & '0';
-			else
-				vld_pipe		<= '0' & vld_pipe(vld_pipe'left downto 1);
+				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
 			end if;
 		end if;
 	end if;
@@ -106,16 +102,36 @@ end process;
 process(clk)
 begin
 	if rising_edge(clk) then
+		if dout_en = '1' then
+			if pre_fin = '1' and din_vld_reg = '1' then
+				shift_pipe		<= din_reg;
+			else	
+				if (msb_first) then
+					shift_pipe		<= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
+				else
+					shift_pipe		<= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
 		if rst = '1' then
-			rdy	<= '0';
-		elsif rdy = '1' then
-			if pre_fin = '1' then
-				if din_vld = '1' then
-					rdy	<= '0';
+			vld_pipe	<= (others => '0');
+		elsif dout_en = '1' then
+			if pre_fin = '1' and din_vld_reg = '1' then
+				vld_pipe		<= din_be_reg;
+			else
+				if (msb_first) then
+					vld_pipe		<= vld_pipe(vld_pipe'left-1 downto 0) & '0';
+				else
+					vld_pipe		<= '0' & vld_pipe(vld_pipe'left downto 1);
 				end if;
 			end if;
-		elsif pre_fin = '1' then
-			rdy	<= '1';
 		end if;
 	end if;
 end process;