- Intital revision
git-svn-id: http://moon:8086/svn/vhdl/trunk@109 cc03376c-175c-47c8-b038-4cd826a8556b
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:25:45 10/15/05
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-- Design Name:
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-- Module Name: vga_backend - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.vga_types.all;
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entity vga_frontend64 is
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Generic
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(
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sys_freq : integer := 100E6;
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fifo_depth : integer := 2048;
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fifo_almost_full_thresh : natural := 2000;
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fifo_almost_empty_thresh : natural := 48;
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tsvga : vga_timespec_t := ts_vga_800_600_72
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);
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Port
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(
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-- System signals
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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-- JBUS Master signals
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CYC_O : out STD_LOGIC;
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STB_O : out STD_LOGIC;
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WE_O : out STD_LOGIC;
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SEL_O : out unsigned(7 downto 0);
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ACK_I : in STD_LOGIC;
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SRDY_I : in STD_LOGIC;
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MRDY_O : out STD_LOGIC;
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ADDR_O : out unsigned(31 downto 0);
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MDAT_I : in unsigned(63 downto 0);
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MDAT_O : out unsigned(63 downto 0);
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-- JBUS Slave signals
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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SDAT_I : in unsigned(31 downto 0);
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SDAT_O : out unsigned(31 downto 0);
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-- VGA signals
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vga_clk_out : out std_logic;
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vga_red : out unsigned(7 downto 0);
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vga_green : out unsigned(7 downto 0);
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vga_blue : out unsigned(7 downto 0);
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vga_blank_n : out std_logic;
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vga_sync_n : out std_logic;
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vga_hsync : out std_logic;
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vga_vsync : out std_logic
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);
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end vga_frontend64;
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architecture Behavioral of vga_frontend64 is
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signal vga_clk : std_logic;
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-- Color FIFO signals
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_almost_empty : std_logic;
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signal fifo_almost_full : std_logic;
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signal fifo_color_re : std_logic;
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signal fifo_color_we : std_logic;
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signal fifo_color_out : unsigned(63 downto 0);
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signal fifo_color_in : unsigned(63 downto 0);
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-- Backend signals
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signal scan_rdy : std_logic;
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signal ctrl_scan_en : std_logic;
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signal color_in : color_array_t;
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signal color_op : color_op_t;
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signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
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signal stat_vga_rdy : std_logic;
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signal stat_hready : std_logic;
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signal stat_vready : std_logic;
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signal stat_scan : std_logic;
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signal stat_hscan : std_logic;
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signal stat_vscan : std_logic;
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signal stat_hsync : std_logic;
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signal stat_vsync : std_logic;
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signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1;
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signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1;
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-- CG signals
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signal cg_en : std_logic;
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signal cg_rdy : std_logic;
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signal cg_draw : std_logic;
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signal cg_clr_screen : std_logic;
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signal cg_clr_line : std_logic;
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signal cg_ascii_data : unsigned(7 downto 0);
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signal cg_ascii_data_we : std_logic;
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signal cg_ascii_posy_we : std_logic;
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signal cg_ascii_posx_we : std_logic;
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-- Bus master signals
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constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
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signal vga_mem_offset : unsigned(31 downto 0);
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signal vga_scan_rdy : std_logic;
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signal vga_master_en : std_logic;
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signal request_cnt_rst : std_logic;
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signal request_cnt_en : std_logic;
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signal pixel_cnt_rst : std_logic;
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signal read_bus_en : std_logic;
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signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1;
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signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1;
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signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
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type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
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signal s, sn : vm_state_t;
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begin
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vga_clk_out <= vga_clk;
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inst_vga_backend : entity work.vga_backend
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GENERIC MAP
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(
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sys_freq => sys_freq,
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tsvga => tsvga
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)
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PORT MAP
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(
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-- System signals
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sys_rst => RST_I,
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sys_clk => CLK_I,
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-- Color channels
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color_in => color_in,
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color_op => color_op,
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color_en => color_en,
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-- Control signals
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ctrl_scan_en => ctrl_scan_en,
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-- Status signals
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stat_vga_rdy => stat_vga_rdy,
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stat_scan => stat_scan,
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stat_hsync => stat_hsync,
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stat_vsync => stat_vsync,
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stat_hready => stat_hready,
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stat_vready => stat_vready,
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stat_hscan => stat_hscan,
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stat_vscan => stat_vscan,
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stat_hpos => stat_hpos,
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stat_vpos => stat_vpos,
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-- VGA domain signals
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vga_clk_out => vga_clk,
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vga_red => vga_red,
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vga_green => vga_green,
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vga_blue => vga_blue,
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vga_blank_n => vga_blank_n,
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vga_sync_n => vga_sync_n,
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vga_hsync => vga_hsync,
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vga_vsync => vga_vsync
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);
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odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length);
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ctrl_scan_en <= '1';
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color_en(0) <= not fifo_empty;
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color_en(1) <= cg_draw;
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color_in(0) <= to_color_t(fifo_color_out(31 downto 0)) when odd_pixel(0) = '0' else to_color_t(fifo_color_out(63 downto 32));
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color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque
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color_op <= op_over;
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vga_scan_rdy <= stat_hready and stat_vready;
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inst_linefifo: entity work.fifo_async
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GENERIC MAP
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(
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addr_width => NextExpBaseTwo(fifo_depth),
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data_width => 64,
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almost_full_thresh => fifo_almost_full_thresh,
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almost_empty_thresh => fifo_almost_empty_thresh
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)
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PORT MAP
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(
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rst => RST_I,
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clk_w => CLK_I,
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clk_r => vga_clk,
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we_w => fifo_color_we,
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re_r => fifo_color_re,
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data_w => fifo_color_in,
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data_r => fifo_color_out,
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fifo_full => fifo_full,
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fifo_empty => fifo_empty,
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fifo_afull => fifo_almost_full,
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fifo_aempty => fifo_almost_empty
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);
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fifo_color_in <= MDAT_I;
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fifo_color_re <= stat_scan and odd_pixel(0);
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fifo_color_we <= ACK_I and read_bus_en; -- TODO:
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MRDY_O <= not fifo_full;
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SEL_O <= (others => '0');
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WE_O <= '0';
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vga_master_next:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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s <= init;
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else
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s <= sn;
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end if;
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end if;
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end process;
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vga_master:
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process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
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begin
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CYC_O <= '0';
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STB_O <= '0';
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pixel_cnt_rst <= '0';
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request_cnt_rst <= '0';
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request_cnt_en <= '0';
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read_bus_en <= '0';
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sn <= s;
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case s is
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when init =>
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if stat_vga_rdy = '1' then
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sn <= idle;
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end if;
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when idle =>
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pixel_cnt_rst <= '1';
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if vga_master_en = '1' and vga_scan_rdy = '1' then
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sn <= rdy;
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end if;
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when rdy =>
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-- pixel_cnt_rst <= '1';
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if fifo_almost_empty = '1' then
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sn <= bus_request;
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end if;
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when bus_request =>
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CYC_O <= '1';
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request_cnt_rst <= '1';
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if SRDY_I = '1' then
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sn <= bus_access;
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end if;
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when bus_access =>
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CYC_O <= '1';
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STB_O <= '1';
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request_cnt_en <= '1';
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read_bus_en <= '1';
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if fifo_almost_full = '1' then
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sn <= bus_data;
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end if;
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when bus_data =>
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CYC_O <= '1';
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read_bus_en <= '1';
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if read_cnt = request_cnt then
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sn <= rdy;
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if vga_master_en = '0' then
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sn <= idle;
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end if;
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end if;
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when others =>
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sn <= idle;
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end case;
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end process;
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request_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if request_cnt_rst = '1' then
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request_cnt <= 0;
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elsif request_cnt_en = '1' and SRDY_I = '1' then
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if request_cnt /= MAX_REQUEST_CNT-1 then
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request_cnt <= request_cnt + 1;
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end if;
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end if;
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end if;
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end process;
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read_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if request_cnt_rst = '1' then
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read_cnt <= 0;
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elsif read_bus_en = '1' and ACK_I = '1' then
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if read_cnt /= MAX_REQUEST_CNT-1 then
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read_cnt <= read_cnt + 1;
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end if;
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end if;
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end if;
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end process;
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pixel_counter:
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process(CLK_I)
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variable pixel_cntx : natural range 0 to tsvga.ts_h.ncyc_scan/2-1;
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variable pixel_cnty : natural range 0 to tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
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begin
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if rising_edge(CLK_I) then
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if pixel_cnt_rst = '1' then
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pixel_cntx := 0;
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pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
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elsif request_cnt_en = '1' and SRDY_I = '1' then
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if pixel_cntx /= tsvga.ts_h.ncyc_scan/2-1 then
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pixel_cntx := pixel_cntx + 1;
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else
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pixel_cntx := 0;
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if pixel_cnty /= 0 then
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pixel_cnty := pixel_cnty - tsvga.ts_h.ncyc_scan;
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else
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pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
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end if;
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end if;
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end if;
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ADDR_O <= vga_mem_offset + (to_unsigned(pixel_cntx, 29) & "000") + (to_unsigned(pixel_cnty, 30) & "00");
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end if;
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end process;
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inst_char_gen : entity work.char_gen
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GENERIC MAP
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(
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tsvga => tsvga,
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CHARACTER_SCALE => 1,
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CHAR_ROM_SIZE_X => 8, -- Pixels
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CHAR_ROM_SIZE_Y => 16, -- Pixels
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CHAR_ROM_DEPTH => 256, -- Chars
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MAX_CHAR_PER_LINE => 80, -- Chars
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MAX_LINE_PER_FRAME => 32, -- Chars
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CHAR_SPACING_X => 0, -- Pixels
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CHAR_SPACING_Y => 0, -- Pixels
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SCREEN_OFFSET_X => 16, -- Pixels
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SCREEN_OFFSET_Y => 16 -- Pixels
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)
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PORT MAP
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(
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rst => RST_I,
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sys_clk => CLK_I,
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vga_clk => vga_clk,
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ce => cg_en,
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frame_pulse => scan_rdy,
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clr_screen => cg_clr_screen,
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clr_line => cg_clr_line,
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ascii_data => cg_ascii_data,
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ascii_data_we => cg_ascii_data_we,
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ascii_posy_we => cg_ascii_posy_we,
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ascii_posx_we => cg_ascii_posx_we,
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ready => cg_rdy,
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pos_x => stat_hpos,
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pos_y => stat_vpos,
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char_draw_en => cg_draw
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);
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SRDY_O <= CYC_I; -- and cg_rdy;
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cg_ascii_data <= SDAT_I(7 downto 0);
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cg_ascii_data_we <= ADDR_I(2) and CYC_I and STB_I and WE_I;
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cg_ascii_posy_we <= ADDR_I(3) and CYC_I and STB_I and WE_I;
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cg_ascii_posx_we <= ADDR_I(4) and CYC_I and STB_I and WE_I;
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cg_clr_screen <= ADDR_I(5) and CYC_I and STB_I and WE_I;
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cg_clr_line <= ADDR_I(6) and CYC_I and STB_I and WE_I;
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SDAT_O <= X"0000000" & "000" & cg_rdy;
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scan_rdy <= stat_hready and stat_vready;
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cg_en <= stat_scan;
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data_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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ACK_O <= '0';
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else
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ACK_O <= CYC_I and STB_I and not WE_I;
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end if;
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end if;
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end process;
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data_valid_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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vga_master_en <= '0';
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vga_mem_offset <= X"40000000";
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elsif (CYC_I and STB_I and WE_I) = '1' then
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if ADDR_I(8) = '1' then
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vga_master_en <= SDAT_I(0);
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elsif ADDR_I(9) = '1' then
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vga_mem_offset <= SDAT_I(31 downto 2) & "00";
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end if;
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end if;
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end if;
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end process;
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---------------------------------------------------------------------------------------------
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end Behavioral;
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