diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo
new file mode 100644
index 0000000..c8fff02
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo
@@ -0,0 +1,28 @@
+## NOTE: Do not edit this file.
+##
+
+vlib work
+vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
+vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
+vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_config.vhd"
+vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_cmd.vhd"
+vcom -explicit -93 "../src/sdram_ctrl.vhd"
+vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_frontend64_wb.vhd"
+vcom -explicit -93 "../src/mt46v16m16.vhd"
+vcom -explicit -93 "../src/tb_sdram_ctrl_frontend64_wb.vhd"
+
+#restart -force
+vsim -t 1ps -lib work tb_sdram_ctrl_frontend64_wb
+do {tb_sdram_ctrl_frontend64_wb.wdo}
+view wave
+view structure
+view signals
+run 200us
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo
new file mode 100644
index 0000000..419220a
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo
@@ -0,0 +1,50 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/rst_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/cyc_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/stb_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/we_o
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sel_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/ack_i
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/mrdy_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt
+add wave -noupdate -divider Part
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cs_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_we_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_ras_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cas_n
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_ba
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dm
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dqs
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {34438503 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {210 us}
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
new file mode 100644
index 0000000..6f8a5fd
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
@@ -0,0 +1,272 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_ctrl_frontend64_wb is
+ Generic
+ (
+ BL : natural := 2;
+ f_sysclk : natural := 100E6;
+ fifo_depth : integer := 4
+ );
+ Port
+ (
+ RST_I : in STD_LOGIC;
+ CLK_I : in STD_LOGIC;
+ CLK270_I : in STD_LOGIC;
+ CLK270VAR_I : in STD_LOGIC;
+
+ CYC_I : in STD_LOGIC;
+ STB_I : in STD_LOGIC;
+ SEL_I : in unsigned(SDR_DM_WIDTH-1 downto 0);
+ WE_I : in STD_LOGIC;
+ ACK_O : out STD_LOGIC;
+ MRDY_I : in STD_LOGIC;
+ SRDY_O : out STD_LOGIC;
+ ADDR_I : in unsigned(31 downto 0);
+ DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0);
+ DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0);
+
+ -- SDRAM signals
+ sd_clk_p : out STD_LOGIC;
+ sd_clk_n : out STD_LOGIC;
+ sd_cke : out STD_LOGIC;
+ sd_cs_n : out STD_LOGIC;
+ sd_cas_n : out STD_LOGIC;
+ sd_ras_n : out STD_LOGIC;
+ sd_we_n : out STD_LOGIC;
+ sd_addr : out sdr_addr_t;
+ sd_ba : out sdr_ba_t;
+ sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
+ sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+ sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
+
+ );
+end sdram_ctrl_frontend64_wb;
+
+architecture struct of sdram_ctrl_frontend64_wb is
+
+ -- Number of user data words for simulation
+ signal u_addr : user_addr_t;
+ signal u_tag_in : user_tag_t;
+ signal u_tag_rd : user_tag_t;
+ signal u_tag_wr : user_tag_t;
+ signal u_cmd : user_cmd_t;
+ signal u_cmd_we : std_logic;
+ signal u_busy : std_logic;
+ signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0);
+ signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal u_data_vld : std_logic;
+ signal u_req_wr : std_logic;
+ signal rdy : std_logic;
+
+ constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
+ signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
+ signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
+ signal cat_fifo_re : std_logic;
+ signal cat_fifo_we : std_logic;
+ signal cat_fifo_full : std_logic;
+ signal cat_fifo_empty : std_logic;
+-- signal cat_fifo_almost_full : std_logic;
+-- signal cat_fifo_almost_empty : std_logic;
+
+ signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
+ signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
+ signal write_fifo_re : std_logic;
+ signal write_fifo_we : std_logic;
+ signal write_fifo_full : std_logic;
+ signal write_fifo_empty : std_logic;
+-- signal write_fifo_almost_full : std_logic;
+-- signal write_fifo_almost_empty : std_logic;
+
+ signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal read_fifo_re : std_logic;
+ signal read_fifo_we : std_logic;
+ signal read_fifo_full : std_logic;
+ signal read_fifo_empty : std_logic;
+-- signal read_fifo_almost_full : std_logic;
+-- signal read_fifo_almost_empty : std_logic;
+
+ alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+ alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+ alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+ alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+ alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+ alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+
+ alias write_fifo_dm_in is write_fifo_din(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
+ alias write_fifo_data_in is write_fifo_din(SDR_DATA_WIDTH-1 downto 0);
+ alias write_fifo_dm_out is write_fifo_dout(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
+ alias write_fifo_data_out is write_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
+
+ alias read_fifo_data_in is read_fifo_din(SDR_DATA_WIDTH-1 downto 0);
+ alias read_fifo_data_out is read_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
+
+begin
+
+ -- Instantiate synchronous FIFO
+ inst_cat_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => fifo_depth,
+ data_width => CAT_FIFO_WIDTH
+ )
+ PORT MAP
+ (
+ rst => RST_I,
+ clk => CLK_I,
+ we => cat_fifo_we,
+ re => cat_fifo_re,
+ fifo_full => cat_fifo_full,
+ fifo_empty => cat_fifo_empty,
+ fifo_afull => open,
+ fifo_aempty => open,
+ data_w => cat_fifo_din,
+ data_r => cat_fifo_dout
+ );
+
+ -- Instantiate synchronous FIFO
+ inst_write_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => fifo_depth,
+ data_width => write_fifo_din'length
+ )
+ PORT MAP
+ (
+ rst => RST_I,
+ clk => CLK_I,
+ we => write_fifo_we,
+ re => write_fifo_re,
+ fifo_full => write_fifo_full,
+ fifo_empty => write_fifo_empty,
+ fifo_afull => open,
+ fifo_aempty => open,
+ data_w => write_fifo_din,
+ data_r => write_fifo_dout
+ );
+
+ -- Instantiate synchronous FIFO
+ inst_read_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => fifo_depth,
+ data_width => read_fifo_din'length
+ )
+ PORT MAP
+ (
+ rst => RST_I,
+ clk => CLK_I,
+ we => read_fifo_we,
+ re => read_fifo_re,
+ fifo_full => read_fifo_full,
+ fifo_empty => read_fifo_empty,
+ fifo_afull => open,
+ fifo_aempty => open,
+ data_w => read_fifo_din,
+ data_r => read_fifo_dout
+ );
+
+ -- DDR SDRAM Controller Core
+ inst_sdram_ctrl : entity work.sdram_ctrl_top
+ Generic map
+ (
+ BL => BL,
+ f_sysclk => f_sysclk
+ )
+ Port map
+ (
+
+ sys_rst_in => RST_I,
+ sys_clk0_in => CLK_I,
+
+ sys_clk270_in => CLK270_I,
+ capture_clk270_in => CLK270VAR_I,
+
+ -- User interface
+ u_data_vld => u_data_vld,
+ u_data_req_w => u_req_wr,
+ u_data_req_r => open,
+ u_tag_in => u_tag_in,
+ u_tag_rd => u_tag_rd,
+ u_tag_wr => u_tag_wr,
+ u_busy => u_busy,
+ u_addr => u_addr,
+ u_cmd => u_cmd,
+ u_cmd_we => u_cmd_we,
+ u_data_wr => u_data_w,
+ u_data_rd => u_data_r,
+ u_dm => u_dm_wr_in,
+
+ -- SDRAM signals
+ sd_clk_p => sd_clk_p,
+ sd_clk_n => sd_clk_n,
+ sd_cke => sd_cke,
+ sd_cs_n => sd_cs_n,
+ sd_cas_n => sd_cas_n,
+ sd_ras_n => sd_ras_n,
+ sd_we_n => sd_we_n,
+ sd_addr => sd_addr,
+ sd_ba => sd_ba,
+ sd_dm => sd_dm,
+ sd_dqs => sd_dqs,
+ sd_data => sd_data
+
+ );
+
+------------------------------------------------------------------------------------------
+ SRDY_O <= rdy;
+ ACK_O <= not (read_fifo_empty);
+ DAT_O <= read_fifo_data_out;
+ rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
+ write_fifo_we <= STB_I and WE_I and rdy;
+ write_fifo_data_in <= DAT_I;
+ write_fifo_dm_in <= not SEL_I;
+ cat_fifo_we <= STB_I and rdy;
+ cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ;
+ addr_fifo_in <= ADDR_I(25 downto 3) & "0";
+ tag_fifo_in <= "000" & ADDR_I(2);
+
+ u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
+ u_cmd <= cmd_fifo_out;
+ u_addr <= addr_fifo_out;
+ u_dm_wr_in <= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when u_tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
+ u_tag_in <= tag_fifo_out;
+ u_data_w <= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when u_tag_wr(0) = '1' else write_fifo_data_out(63 downto 0);
+
+ write_fifo_re <= u_req_wr and (not write_fifo_empty);
+ cat_fifo_re <= u_cmd_we;
+ read_fifo_re <= (not read_fifo_empty) and MRDY_I;
+ read_fifo_we <= u_data_vld;
+ read_fifo_data_in <= (u_data_r(31 downto 0) & u_data_r(63 downto 32)) when u_tag_rd(0) = '1' else u_data_r(63 downto 0);
+
+end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
new file mode 100644
index 0000000..1805da3
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
@@ -0,0 +1,860 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity tb_sdram_ctrl_frontend64_wb is
+end;
+
+architecture struct of tb_sdram_ctrl_frontend64_wb is
+
+ -- Number of user data words for simulation
+ constant CLK_PERIOD : time := 10 ns;
+ constant BURST_LEN : natural := 2;
+
+ signal rst : std_logic := '1';
+ signal clk : std_logic := '1';
+ signal locked : std_logic;
+ signal error : std_logic;
+ signal clk_out : std_logic;
+ signal clk_fb : std_logic;
+ signal part_clk_p : std_logic;
+ signal part_clk_n : std_logic;
+ signal part_cke : std_logic;
+ signal part_cs_n : std_logic;
+ signal part_we_n : std_logic;
+ signal part_ras_n : std_logic;
+ signal part_cas_n : std_logic;
+ signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+ signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+ signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+ signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ signal CLK_O : std_logic;
+ signal CLK270_O : std_logic;
+ signal CLK270VAR_O : std_logic;
+ signal RST_O : std_logic;
+ signal CYC_O : std_logic := '0';
+ signal STB_O : std_logic := '0';
+ signal WE_O : std_logic := '0';
+ signal SEL_O : unsigned(SDR_DM_WIDTH-1 downto 0);
+ signal ACK_I : std_logic;
+ signal MRDY_O : std_logic := '1';
+ signal SRDY_I : std_logic;
+ signal ADDR_O : unsigned(31 downto 0) := (others => '-');
+ signal DAT_I : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal DAT_O : unsigned(SDR_DATA_WIDTH-1 downto 0);
+
+ signal dout_rst : std_logic := '0';
+ signal dout_reg : unsigned(31 downto 0);
+ signal dout_cnt : natural range 0 to 255;
+
+ signal sddat : unsigned(31 downto 0) := (others => '-');
+ signal sdsel : unsigned(3 downto 0) := (others => '1');
+
+ type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
+ signal sd_cmd : sd_cmd_t;
+
+begin
+
+ process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
+ variable cmd : unsigned (2 downto 0);
+
+ begin
+ cmd := part_ras_n & part_cas_n & part_we_n;
+ sd_cmd <= nop;
+ if part_cs_n = '0' then
+ case cmd is
+ when "000" =>
+ sd_cmd <= lmr;
+ when "001" =>
+ sd_cmd <= ar;
+ when "010" =>
+ sd_cmd <= pre;
+ when "011" =>
+ sd_cmd <= act;
+ when "100" =>
+ sd_cmd <= write;
+ when "101" =>
+ sd_cmd <= read;
+ when "110" =>
+ sd_cmd <= bst;
+ when "111" =>
+ sd_cmd <= nop;
+
+ when others =>
+ sd_cmd <= nop;
+
+ end case;
+ end if;
+ end process;
+
+inst_clockgen : entity work.clockgen
+ GENERIC MAP
+ (
+ sys1_phaseshift => 0,
+ frequency_hz => 100E6
+ )
+ PORT MAP
+ (
+ -- Clocks and Reset
+ rst => rst, -- external async reset, low active
+ clk_in => clk, -- system clock (e.g. 100MHz), from board
+ clk_fb_in => clk_fb, -- feedback clock
+ sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+ sys1_clk270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+ sys0_clk0_out => CLK_O, -- System clock #0, dcm#0 output 0°
+ sys0_clk270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
+ locked_out => locked, -- DCM locked status
+ error_out => error
+ );
+
+
+ clk_fb <= part_clk_p after 1 ns;
+ RST_O <= not locked;
+ DAT_O <= X"DEADBEEF" & sddat;
+ SEL_O <= "0000" & sdsel;
+
+ -- DDR SDRAM Controller Core
+ sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
+ GENERIC MAP
+ (
+ BL => BURST_LEN,
+ f_sysclk => 100E6,
+ fifo_depth => 3
+ )
+ PORT MAP
+ (
+ RST_I => RST_O,
+ CLK_I => CLK_O,
+ CLK270_I => CLK270_O,
+ CLK270VAR_I => CLK270VAR_O,
+
+ CYC_I => CYC_O,
+ STB_I => STB_O,
+ SEL_I => SEL_O,
+ WE_I => WE_O,
+ ACK_O => ACK_I,
+ SRDY_O => SRDY_I,
+ MRDY_I => MRDY_O,
+ ADDR_I => ADDR_O,
+ DAT_I => DAT_O,
+ DAT_O => DAT_I,
+
+ -- SDRAM signals
+ sd_clk_p => part_clk_p,
+ sd_clk_n => part_clk_n,
+ sd_cke => part_cke,
+ sd_cs_n => part_cs_n,
+ sd_cas_n => part_cas_n,
+ sd_ras_n => part_ras_n,
+ sd_we_n => part_we_n,
+ sd_addr => part_addr,
+ sd_ba => part_ba,
+ sd_dm => part_dm,
+ sd_dqs => part_dqs,
+ sd_data => part_data
+
+ );
+
+ -- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_0 : entity work.mt46v16m16
+ port map
+ (
+ dq => std_logic_vector(part_data(15 downto 0)),
+ dqs => std_logic_vector(part_dqs(1 downto 0)),
+ addr => std_logic_vector(part_addr),
+ ba => std_logic_vector(part_ba),
+ clk => part_clk_p,
+ clk_n => part_clk_n,
+ cke => part_cke,
+ cs_n => part_cs_n,
+ ras_n => part_ras_n,
+ cas_n => part_cas_n,
+ we_n => part_we_n,
+ dm => std_logic_vector(part_dm(1 downto 0))
+ );
+
+ -- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_1 : entity work.mt46v16m16
+ port map
+ (
+ dq => std_logic_vector(part_data(31 downto 16)),
+ dqs => std_logic_vector(part_dqs(3 downto 2)),
+ addr => std_logic_vector(part_addr),
+ ba => std_logic_vector(part_ba),
+ clk => part_clk_p,
+ clk_n => part_clk_n,
+ cke => part_cke,
+ cs_n => part_cs_n,
+ ras_n => part_ras_n,
+ cas_n => part_cas_n,
+ we_n => part_we_n,
+ dm => std_logic_vector(part_dm(3 downto 2))
+ );
+
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ clk <= not clk;
+ end process;
+
+read_register:
+ process(CLK_O)
+ begin
+ if rising_edge(CLK_O) then
+ if dout_rst = '1' then
+ dout_cnt <= 0;
+ elsif ACK_I = '1' and WE_O = '0' then
+ dout_reg <= DAT_I(31 downto 0);
+ dout_cnt <= dout_cnt + 1;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+
+STIMULUS: process
+
+ begin
+
+ wait for 3*CLK_PERIOD;
+ rst <= '0';
+
+ wait until RST_O = '0';
+ -- 8 single cycles
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sddat <= X"1234_0000";
+ ADDR_O <= X"0000_0000";
+
+ for i in 0 to 8192 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ sddat <= sddat + 1;
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+ wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_0000";
+
+ for i in 0 to 31 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 31;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+ wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ wait until rising_edge(CLK_O);
+ -- 1-word burst cycle
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sdsel <= "0011";
+ ADDR_O <= X"0000_0080";
+ sddat <= X"DEADBEEF";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+ wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ wait until rising_edge(CLK_O);
+ -- 1-word burst cycle
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_0080";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and ACK_I = '1';
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+ wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_0000";
+
+ for i in 0 to 31 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 31;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+ wait for 10*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ for k in 0 to 3 loop
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_0000";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_0400";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_0800";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_0C00";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ end loop;
+
+ ------------------------------------------------------------
+ wait for 10*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ for k in 0 to 3 loop
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_1000";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_1400";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_1800";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_1C00";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ end loop;
+
+ ------------------------------------------------------------
+ wait for 10*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ for k in 0 to 3 loop
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sdsel <= "1111";
+ sddat <= X"1111_0000";
+ ADDR_O <= X"0000_0000";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ sddat <= sddat + 1;
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sdsel <= "1111";
+ sddat <= X"2222_0000";
+ ADDR_O <= X"0000_0400";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ sddat <= sddat + 1;
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sdsel <= "1111";
+ sddat <= X"3333_0000";
+ ADDR_O <= X"0000_0800";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ sddat <= sddat + 1;
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sdsel <= "1111";
+ sddat <= X"4444_0000";
+ ADDR_O <= X"0000_0C00";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ sddat <= sddat + 1;
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ end loop;
+
+ ------------------------------------------------------------
+ wait for 10*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ for k in 0 to 3 loop
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sdsel <= "1111";
+ sddat <= X"1111_0000";
+ ADDR_O <= X"0000_1000";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ sddat <= sddat + 1;
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sdsel <= "1111";
+ sddat <= X"2222_0000";
+ ADDR_O <= X"0000_1400";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ sddat <= sddat + 1;
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sdsel <= "1111";
+ sddat <= X"3333_0000";
+ ADDR_O <= X"0000_1800";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ sddat <= sddat + 1;
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ sdsel <= "1111";
+ sddat <= X"4444_0000";
+ ADDR_O <= X"0000_1C00";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ sddat <= sddat + 1;
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+ end loop;
+
+ ------------------------------------------------------------
+ wait for 10*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ for k in 0 to 3 loop
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_1000";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_1400";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_1800";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ ------------------------------------------------------------
+-- wait for 3*CLK_PERIOD;
+ ------------------------------------------------------------
+
+ -- 8-word burst cycle
+ dout_rst <= '1';
+ wait until rising_edge(CLK_O);
+ dout_rst <= '0';
+
+ CYC_O <= '1';
+ STB_O <= '1';
+ WE_O <= '0';
+ ADDR_O <= X"0000_1C00";
+
+ for i in 0 to 7 loop
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ ADDR_O <= ADDR_O + 4;
+ end loop;
+
+ STB_O <= '0';
+ wait until rising_edge(CLK_O) and dout_cnt = 7;
+ CYC_O <= '0';
+
+ end loop;
+
+ wait;
+
+ end process;
+
+end architecture struct;
diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
new file mode 100644
index 0000000..95ab71e
--- /dev/null
+++ b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
@@ -0,0 +1,25 @@
+## NOTE: Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
+vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
+vcom -explicit -93 "../../FIFO/src/async_fifo_ctrl.vhd"
+vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
+vcom -explicit -93 "../src/fonts/char_rom_c64.vhd"
+vcom -explicit -93 "../src/vga_types.vhd"
+vcom -explicit -93 "../src/clkgen_virtex4.vhd"
+vcom -explicit -93 "../src/char_gen.vhd"
+vcom -explicit -93 "../src/vga_sync.vhd"
+vcom -explicit -93 "../src/vga_timing.vhd"
+vcom -explicit -93 "../src/vga_backend.vhd"
+vcom -explicit -93 "../src/vga_frontend64.vhd"
+vcom -explicit -93 "../src/tb_vga_frontend64.vhd"
+vsim -t 1ps -lib work tb_vga_frontend64
+view wave
+do {tb_vga_frontend64.wdo}
+view structure
+view signals
+
+run 20ms
diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo
new file mode 100644
index 0000000..a73a3f1
--- /dev/null
+++ b/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo
@@ -0,0 +1,65 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
+add wave -noupdate -format Logic /tb_vga_frontend64/rst_o
+add wave -noupdate -divider Master
+add wave -noupdate -format Logic /tb_vga_frontend64/cyc_o
+add wave -noupdate -format Logic /tb_vga_frontend64/stb_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/addr_o
+add wave -noupdate -format Literal /tb_vga_frontend64/sel_o
+add wave -noupdate -format Logic /tb_vga_frontend64/we_o
+add wave -noupdate -format Logic /tb_vga_frontend64/ack_i
+add wave -noupdate -format Logic /tb_vga_frontend64/mrdy_o
+add wave -noupdate -format Logic /tb_vga_frontend64/srdy_i
+add wave -noupdate -divider Slave
+add wave -noupdate -format Logic /tb_vga_frontend64/cyc_i
+add wave -noupdate -format Logic /tb_vga_frontend64/stb_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/addr_i
+add wave -noupdate -format Literal /tb_vga_frontend64/sel_i
+add wave -noupdate -format Logic /tb_vga_frontend64/we_i
+add wave -noupdate -format Logic /tb_vga_frontend64/ack_o
+add wave -noupdate -format Logic /tb_vga_frontend64/mrdy_i
+add wave -noupdate -format Logic /tb_vga_frontend64/srdy_o
+add wave -noupdate -divider VGA
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_clk_out
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_blank_n
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_sync_n
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_hsync
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_vsync
+add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_red
+add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_green
+add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_blue
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/request_cnt
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/read_cnt
+add wave -noupdate -divider Backend
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/ctrl_scan_en
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/sys_rst
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_vga_rdy
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_scan
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/scan_enable
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/is_scan
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_hpos
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_vpos
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/rst
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/dcm_locked
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_draw
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_en
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/hready
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/vready
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1420398899 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {1382189057 ps} {1476673938 ps}
diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
new file mode 100644
index 0000000..279f854
--- /dev/null
+++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
@@ -0,0 +1,201 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+use work.vga_types.all;
+
+ENTITY tb_vga_frontend64 IS
+END tb_vga_frontend64;
+
+ARCHITECTURE behavior OF tb_vga_frontend64 IS
+
+ constant CLK_PERIOD : time := 10 ns;
+ signal CLK_O : std_logic := '1';
+ signal RST_O : std_logic := '1';
+
+ -- Master
+ signal CYC_O : std_logic;
+ signal STB_O : std_logic;
+ signal WE_O : std_logic;
+ signal SEL_O : unsigned(3 downto 0) := (others => '1');
+ signal ACK_I : std_logic := '0';
+ signal MRDY_O : std_logic := '1';
+ signal SRDY_I : std_logic := '0';
+ signal ADDR_O : unsigned(31 downto 0);
+ signal MDAT_I : unsigned(63 downto 0);
+ signal MDAT_O : unsigned(63 downto 0);
+
+ -- Slave
+ signal CYC_I : std_logic := '0';
+ signal STB_I : std_logic := '0';
+ signal WE_I : std_logic := '0';
+ signal SEL_I : unsigned(7 downto 0);
+ signal ACK_O : std_logic;
+ signal MRDY_I : std_logic;
+ signal SRDY_O : std_logic;
+ signal ADDR_I : unsigned(31 downto 0) := (others => '-');
+ signal SDAT_I : unsigned(31 downto 0) := (others => '-');
+ signal SDAT_O : unsigned(31 downto 0);
+
+ -- VGA signals
+ signal vga_clk_out : std_logic;
+ signal vga_red : unsigned(7 downto 0);
+ signal vga_green : unsigned(7 downto 0);
+ signal vga_blue : unsigned(7 downto 0);
+ signal vga_blank_n : std_logic;
+ signal vga_sync_n : std_logic;
+ signal vga_hsync : std_logic;
+ signal vga_vsync : std_logic;
+
+BEGIN
+
+inst_vga_frontend64 : entity work.vga_frontend64
+ GENERIC MAP
+ (
+ sys_freq => 100E6,
+ fifo_depth => 2048,
+ fifo_almost_full_thresh => 2000,
+ fifo_almost_empty_thresh => 48,
+ tsvga => ts_vga_800_600_72
+ )
+ PORT MAP
+ (
+ -- System signals
+ RST_I => RST_O,
+ CLK_I => CLK_O,
+
+ -- JBUS Master signals
+ CYC_O => CYC_I,
+ STB_O => STB_I,
+ WE_O => WE_I,
+ SEL_O => SEL_I,
+ ACK_I => ACK_O,
+ SRDY_I => SRDY_O,
+ MRDY_O => MRDY_I,
+ ADDR_O => ADDR_I,
+ MDAT_I => MDAT_O,
+ MDAT_O => MDAT_I,
+
+ -- JBUS Slave signals
+ CYC_I => CYC_O,
+ STB_I => STB_O,
+ WE_I => WE_O,
+ SEL_I => SEL_O,
+ ACK_O => ACK_I,
+ SRDY_O => SRDY_I,
+ MRDY_I => MRDY_O,
+ ADDR_I => ADDR_O,
+ SDAT_I => SDAT_O,
+ SDAT_O => SDAT_I,
+
+ -- VGA signals
+ vga_clk_out => vga_clk_out,
+ vga_red => vga_red,
+ vga_green => vga_green,
+ vga_blue => vga_blue,
+ vga_blank_n => vga_blank_n,
+ vga_sync_n => vga_sync_n,
+ vga_hsync => vga_hsync,
+ vga_vsync => vga_vsync
+ );
+
+
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ CLK_O <= not CLK_O;
+ end process;
+
+-- Slave
+ SRDY_O <= CYC_I;
+
+ process(CLK_O)
+ begin
+ if rising_edge(CLK_O) then
+ if RST_O = '1' then
+ MDAT_O <= X"00000000_00000000";
+ elsif (CYC_I and STB_I) = '1' then
+ MDAT_O <= MDAT_O + 1;
+ ACK_O <= '1';
+ else
+ ACK_O <= '0';
+ end if;
+ end if;
+ end process;
+
+-- Master
+STIMULUS: process
+
+ begin
+
+ wait for 6*CLK_PERIOD;
+ RST_O <= '0';
+
+ -- 8 single cycles
+ CYC_O <= '1';
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_I <= X"0000_0000";
+ ADDR_O <= X"0000_0008";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_I <= X"0000_0000";
+ ADDR_O <= X"0000_0010";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_I <= X"0000_0035";
+ ADDR_O <= X"0000_0004";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '1';
+ WE_O <= '1';
+ SDAT_I <= X"0000_0035";
+ ADDR_O <= X"0000_0020";
+ wait until rising_edge(CLK_O) and SRDY_I = '1';
+ STB_O <= '0';
+
+ wait until rising_edge(CLK_O);
+ CYC_O <= '0';
+
+
+
+ wait;
+
+ end process;
+
+END;
diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd
new file mode 100644
index 0000000..09feec1
--- /dev/null
+++ b/lib/VGA_ctrl/src/vga_frontend64.vhd
@@ -0,0 +1,426 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:25:45 10/15/05
+-- Design Name:
+-- Module Name: vga_backend - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity vga_frontend64 is
+ Generic
+ (
+ sys_freq : integer := 100E6;
+ fifo_depth : integer := 2048;
+ fifo_almost_full_thresh : natural := 2000;
+ fifo_almost_empty_thresh : natural := 48;
+ tsvga : vga_timespec_t := ts_vga_800_600_72
+ );
+ Port
+ (
+ -- System signals
+ RST_I : in STD_LOGIC;
+ CLK_I : in STD_LOGIC;
+
+ -- JBUS Master signals
+ CYC_O : out STD_LOGIC;
+ STB_O : out STD_LOGIC;
+ WE_O : out STD_LOGIC;
+ SEL_O : out unsigned(7 downto 0);
+ ACK_I : in STD_LOGIC;
+ SRDY_I : in STD_LOGIC;
+ MRDY_O : out STD_LOGIC;
+ ADDR_O : out unsigned(31 downto 0);
+ MDAT_I : in unsigned(63 downto 0);
+ MDAT_O : out unsigned(63 downto 0);
+
+ -- JBUS Slave signals
+ CYC_I : in STD_LOGIC;
+ STB_I : in STD_LOGIC;
+ WE_I : in STD_LOGIC;
+ SEL_I : in unsigned(3 downto 0);
+ ACK_O : out STD_LOGIC;
+ SRDY_O : out STD_LOGIC;
+ MRDY_I : in STD_LOGIC;
+ ADDR_I : in unsigned(31 downto 0);
+ SDAT_I : in unsigned(31 downto 0);
+ SDAT_O : out unsigned(31 downto 0);
+
+ -- VGA signals
+ vga_clk_out : out std_logic;
+ vga_red : out unsigned(7 downto 0);
+ vga_green : out unsigned(7 downto 0);
+ vga_blue : out unsigned(7 downto 0);
+ vga_blank_n : out std_logic;
+ vga_sync_n : out std_logic;
+ vga_hsync : out std_logic;
+ vga_vsync : out std_logic
+ );
+end vga_frontend64;
+
+architecture Behavioral of vga_frontend64 is
+
+
+ signal vga_clk : std_logic;
+
+ -- Color FIFO signals
+ signal fifo_full : std_logic;
+ signal fifo_empty : std_logic;
+ signal fifo_almost_empty : std_logic;
+ signal fifo_almost_full : std_logic;
+ signal fifo_color_re : std_logic;
+ signal fifo_color_we : std_logic;
+ signal fifo_color_out : unsigned(63 downto 0);
+ signal fifo_color_in : unsigned(63 downto 0);
+
+ -- Backend signals
+ signal scan_rdy : std_logic;
+ signal ctrl_scan_en : std_logic;
+ signal color_in : color_array_t;
+ signal color_op : color_op_t;
+ signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
+
+ signal stat_vga_rdy : std_logic;
+ signal stat_hready : std_logic;
+ signal stat_vready : std_logic;
+ signal stat_scan : std_logic;
+ signal stat_hscan : std_logic;
+ signal stat_vscan : std_logic;
+ signal stat_hsync : std_logic;
+ signal stat_vsync : std_logic;
+ signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1;
+ signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1;
+
+ -- CG signals
+ signal cg_en : std_logic;
+ signal cg_rdy : std_logic;
+ signal cg_draw : std_logic;
+ signal cg_clr_screen : std_logic;
+ signal cg_clr_line : std_logic;
+ signal cg_ascii_data : unsigned(7 downto 0);
+ signal cg_ascii_data_we : std_logic;
+ signal cg_ascii_posy_we : std_logic;
+ signal cg_ascii_posx_we : std_logic;
+
+ -- Bus master signals
+ constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
+
+ signal vga_mem_offset : unsigned(31 downto 0);
+ signal vga_scan_rdy : std_logic;
+ signal vga_master_en : std_logic;
+ signal request_cnt_rst : std_logic;
+ signal request_cnt_en : std_logic;
+ signal pixel_cnt_rst : std_logic;
+ signal read_bus_en : std_logic;
+ signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1;
+ signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1;
+
+ signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
+
+ type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
+ signal s, sn : vm_state_t;
+
+begin
+
+ vga_clk_out <= vga_clk;
+
+inst_vga_backend : entity work.vga_backend
+ GENERIC MAP
+ (
+ sys_freq => sys_freq,
+ tsvga => tsvga
+ )
+ PORT MAP
+ (
+ -- System signals
+ sys_rst => RST_I,
+ sys_clk => CLK_I,
+
+ -- Color channels
+ color_in => color_in,
+ color_op => color_op,
+ color_en => color_en,
+
+ -- Control signals
+ ctrl_scan_en => ctrl_scan_en,
+
+ -- Status signals
+ stat_vga_rdy => stat_vga_rdy,
+ stat_scan => stat_scan,
+ stat_hsync => stat_hsync,
+ stat_vsync => stat_vsync,
+ stat_hready => stat_hready,
+ stat_vready => stat_vready,
+ stat_hscan => stat_hscan,
+ stat_vscan => stat_vscan,
+ stat_hpos => stat_hpos,
+ stat_vpos => stat_vpos,
+
+ -- VGA domain signals
+ vga_clk_out => vga_clk,
+ vga_red => vga_red,
+ vga_green => vga_green,
+ vga_blue => vga_blue,
+ vga_blank_n => vga_blank_n,
+ vga_sync_n => vga_sync_n,
+ vga_hsync => vga_hsync,
+ vga_vsync => vga_vsync
+ );
+
+ odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length);
+ ctrl_scan_en <= '1';
+ color_en(0) <= not fifo_empty;
+ color_en(1) <= cg_draw;
+ color_in(0) <= to_color_t(fifo_color_out(31 downto 0)) when odd_pixel(0) = '0' else to_color_t(fifo_color_out(63 downto 32));
+ color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque
+ color_op <= op_over;
+ vga_scan_rdy <= stat_hready and stat_vready;
+
+inst_linefifo: entity work.fifo_async
+ GENERIC MAP
+ (
+ addr_width => NextExpBaseTwo(fifo_depth),
+ data_width => 64,
+ almost_full_thresh => fifo_almost_full_thresh,
+ almost_empty_thresh => fifo_almost_empty_thresh
+ )
+ PORT MAP
+ (
+ rst => RST_I,
+ clk_w => CLK_I,
+ clk_r => vga_clk,
+ we_w => fifo_color_we,
+ re_r => fifo_color_re,
+ data_w => fifo_color_in,
+ data_r => fifo_color_out,
+ fifo_full => fifo_full,
+ fifo_empty => fifo_empty,
+ fifo_afull => fifo_almost_full,
+ fifo_aempty => fifo_almost_empty
+
+ );
+
+ fifo_color_in <= MDAT_I;
+ fifo_color_re <= stat_scan and odd_pixel(0);
+ fifo_color_we <= ACK_I and read_bus_en; -- TODO:
+ MRDY_O <= not fifo_full;
+ SEL_O <= (others => '0');
+ WE_O <= '0';
+
+vga_master_next:
+ process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ s <= init;
+ else
+ s <= sn;
+ end if;
+ end if;
+ end process;
+
+vga_master:
+ process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
+ begin
+
+ CYC_O <= '0';
+ STB_O <= '0';
+ pixel_cnt_rst <= '0';
+ request_cnt_rst <= '0';
+ request_cnt_en <= '0';
+ read_bus_en <= '0';
+ sn <= s;
+
+ case s is
+ when init =>
+ if stat_vga_rdy = '1' then
+ sn <= idle;
+ end if;
+
+ when idle =>
+ pixel_cnt_rst <= '1';
+ if vga_master_en = '1' and vga_scan_rdy = '1' then
+ sn <= rdy;
+ end if;
+
+ when rdy =>
+-- pixel_cnt_rst <= '1';
+ if fifo_almost_empty = '1' then
+ sn <= bus_request;
+ end if;
+
+ when bus_request =>
+ CYC_O <= '1';
+ request_cnt_rst <= '1';
+ if SRDY_I = '1' then
+ sn <= bus_access;
+ end if;
+
+ when bus_access =>
+ CYC_O <= '1';
+ STB_O <= '1';
+ request_cnt_en <= '1';
+ read_bus_en <= '1';
+ if fifo_almost_full = '1' then
+ sn <= bus_data;
+ end if;
+ when bus_data =>
+ CYC_O <= '1';
+ read_bus_en <= '1';
+ if read_cnt = request_cnt then
+ sn <= rdy;
+ if vga_master_en = '0' then
+ sn <= idle;
+ end if;
+ end if;
+ when others =>
+ sn <= idle;
+
+ end case;
+ end process;
+
+request_counter:
+ process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if request_cnt_rst = '1' then
+ request_cnt <= 0;
+ elsif request_cnt_en = '1' and SRDY_I = '1' then
+ if request_cnt /= MAX_REQUEST_CNT-1 then
+ request_cnt <= request_cnt + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+read_counter:
+ process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if request_cnt_rst = '1' then
+ read_cnt <= 0;
+ elsif read_bus_en = '1' and ACK_I = '1' then
+ if read_cnt /= MAX_REQUEST_CNT-1 then
+ read_cnt <= read_cnt + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+pixel_counter:
+ process(CLK_I)
+ variable pixel_cntx : natural range 0 to tsvga.ts_h.ncyc_scan/2-1;
+ variable pixel_cnty : natural range 0 to tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
+ begin
+ if rising_edge(CLK_I) then
+ if pixel_cnt_rst = '1' then
+ pixel_cntx := 0;
+ pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
+ elsif request_cnt_en = '1' and SRDY_I = '1' then
+ if pixel_cntx /= tsvga.ts_h.ncyc_scan/2-1 then
+ pixel_cntx := pixel_cntx + 1;
+ else
+ pixel_cntx := 0;
+ if pixel_cnty /= 0 then
+ pixel_cnty := pixel_cnty - tsvga.ts_h.ncyc_scan;
+ else
+ pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
+ end if;
+ end if;
+ end if;
+ ADDR_O <= vga_mem_offset + (to_unsigned(pixel_cntx, 29) & "000") + (to_unsigned(pixel_cnty, 30) & "00");
+ end if;
+ end process;
+
+inst_char_gen : entity work.char_gen
+ GENERIC MAP
+ (
+ tsvga => tsvga,
+ CHARACTER_SCALE => 1,
+ CHAR_ROM_SIZE_X => 8, -- Pixels
+ CHAR_ROM_SIZE_Y => 16, -- Pixels
+ CHAR_ROM_DEPTH => 256, -- Chars
+ MAX_CHAR_PER_LINE => 80, -- Chars
+ MAX_LINE_PER_FRAME => 32, -- Chars
+ CHAR_SPACING_X => 0, -- Pixels
+ CHAR_SPACING_Y => 0, -- Pixels
+ SCREEN_OFFSET_X => 16, -- Pixels
+ SCREEN_OFFSET_Y => 16 -- Pixels
+ )
+ PORT MAP
+ (
+ rst => RST_I,
+ sys_clk => CLK_I,
+ vga_clk => vga_clk,
+ ce => cg_en,
+ frame_pulse => scan_rdy,
+ clr_screen => cg_clr_screen,
+ clr_line => cg_clr_line,
+ ascii_data => cg_ascii_data,
+ ascii_data_we => cg_ascii_data_we,
+ ascii_posy_we => cg_ascii_posy_we,
+ ascii_posx_we => cg_ascii_posx_we,
+ ready => cg_rdy,
+ pos_x => stat_hpos,
+ pos_y => stat_vpos,
+ char_draw_en => cg_draw
+ );
+ SRDY_O <= CYC_I; -- and cg_rdy;
+ cg_ascii_data <= SDAT_I(7 downto 0);
+ cg_ascii_data_we <= ADDR_I(2) and CYC_I and STB_I and WE_I;
+ cg_ascii_posy_we <= ADDR_I(3) and CYC_I and STB_I and WE_I;
+ cg_ascii_posx_we <= ADDR_I(4) and CYC_I and STB_I and WE_I;
+ cg_clr_screen <= ADDR_I(5) and CYC_I and STB_I and WE_I;
+ cg_clr_line <= ADDR_I(6) and CYC_I and STB_I and WE_I;
+ SDAT_O <= X"0000000" & "000" & cg_rdy;
+ scan_rdy <= stat_hready and stat_vready;
+ cg_en <= stat_scan;
+
+data_register:
+ process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ ACK_O <= '0';
+ else
+ ACK_O <= CYC_I and STB_I and not WE_I;
+ end if;
+ end if;
+ end process;
+
+data_valid_register:
+ process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ vga_master_en <= '0';
+ vga_mem_offset <= X"40000000";
+ elsif (CYC_I and STB_I and WE_I) = '1' then
+ if ADDR_I(8) = '1' then
+ vga_master_en <= SDAT_I(0);
+ elsif ADDR_I(9) = '1' then
+ vga_mem_offset <= SDAT_I(31 downto 2) & "00";
+ end if;
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------------------------
+
+end Behavioral;