- Intital revision
git-svn-id: http://moon:8086/svn/vhdl/trunk@109 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,272 @@
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-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: cpu_embedded using cpu_core and rom
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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||||
-- This program is free software: you can redistribute it and/or modify
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||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
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||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
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||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.fifo_ctrl_pkg.all;
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use work.sdram_config.all;
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use work.sdram_types.all;
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entity sdram_ctrl_frontend64_wb is
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Generic
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(
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BL : natural := 2;
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f_sysclk : natural := 100E6;
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fifo_depth : integer := 4
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);
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Port
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(
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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CLK270_I : in STD_LOGIC;
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CLK270VAR_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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SEL_I : in unsigned(SDR_DM_WIDTH-1 downto 0);
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0);
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DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0);
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-- SDRAM signals
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sd_clk_p : out STD_LOGIC;
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sd_clk_n : out STD_LOGIC;
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sd_cke : out STD_LOGIC;
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sd_cs_n : out STD_LOGIC;
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sd_cas_n : out STD_LOGIC;
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sd_ras_n : out STD_LOGIC;
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sd_we_n : out STD_LOGIC;
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sd_addr : out sdr_addr_t;
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sd_ba : out sdr_ba_t;
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sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
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sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
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sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
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);
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end sdram_ctrl_frontend64_wb;
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architecture struct of sdram_ctrl_frontend64_wb is
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-- Number of user data words for simulation
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signal u_addr : user_addr_t;
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signal u_tag_in : user_tag_t;
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signal u_tag_rd : user_tag_t;
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signal u_tag_wr : user_tag_t;
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signal u_cmd : user_cmd_t;
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signal u_cmd_we : std_logic;
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signal u_busy : std_logic;
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signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0);
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signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0);
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signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
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signal u_data_vld : std_logic;
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signal u_req_wr : std_logic;
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signal rdy : std_logic;
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constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
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signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
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signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
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signal cat_fifo_re : std_logic;
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signal cat_fifo_we : std_logic;
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signal cat_fifo_full : std_logic;
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signal cat_fifo_empty : std_logic;
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-- signal cat_fifo_almost_full : std_logic;
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-- signal cat_fifo_almost_empty : std_logic;
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signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
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signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
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signal write_fifo_re : std_logic;
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signal write_fifo_we : std_logic;
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signal write_fifo_full : std_logic;
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signal write_fifo_empty : std_logic;
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-- signal write_fifo_almost_full : std_logic;
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-- signal write_fifo_almost_empty : std_logic;
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signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0);
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signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0);
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signal read_fifo_re : std_logic;
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signal read_fifo_we : std_logic;
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signal read_fifo_full : std_logic;
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signal read_fifo_empty : std_logic;
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-- signal read_fifo_almost_full : std_logic;
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-- signal read_fifo_almost_empty : std_logic;
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alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
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alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
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alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
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alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
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alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
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alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
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alias write_fifo_dm_in is write_fifo_din(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
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alias write_fifo_data_in is write_fifo_din(SDR_DATA_WIDTH-1 downto 0);
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alias write_fifo_dm_out is write_fifo_dout(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
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alias write_fifo_data_out is write_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
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alias read_fifo_data_in is read_fifo_din(SDR_DATA_WIDTH-1 downto 0);
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alias read_fifo_data_out is read_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
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begin
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-- Instantiate synchronous FIFO
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inst_cat_fifo: entity work.fifo_sync
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GENERIC MAP
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(
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addr_width => fifo_depth,
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data_width => CAT_FIFO_WIDTH
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)
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PORT MAP
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(
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rst => RST_I,
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clk => CLK_I,
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we => cat_fifo_we,
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re => cat_fifo_re,
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fifo_full => cat_fifo_full,
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fifo_empty => cat_fifo_empty,
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fifo_afull => open,
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fifo_aempty => open,
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data_w => cat_fifo_din,
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data_r => cat_fifo_dout
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);
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-- Instantiate synchronous FIFO
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inst_write_fifo: entity work.fifo_sync
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GENERIC MAP
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(
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addr_width => fifo_depth,
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data_width => write_fifo_din'length
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)
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PORT MAP
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(
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rst => RST_I,
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clk => CLK_I,
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we => write_fifo_we,
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re => write_fifo_re,
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fifo_full => write_fifo_full,
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fifo_empty => write_fifo_empty,
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fifo_afull => open,
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fifo_aempty => open,
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data_w => write_fifo_din,
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data_r => write_fifo_dout
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);
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-- Instantiate synchronous FIFO
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inst_read_fifo: entity work.fifo_sync
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GENERIC MAP
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(
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addr_width => fifo_depth,
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data_width => read_fifo_din'length
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)
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PORT MAP
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(
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rst => RST_I,
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clk => CLK_I,
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we => read_fifo_we,
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re => read_fifo_re,
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fifo_full => read_fifo_full,
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fifo_empty => read_fifo_empty,
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fifo_afull => open,
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fifo_aempty => open,
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data_w => read_fifo_din,
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data_r => read_fifo_dout
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);
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-- DDR SDRAM Controller Core
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inst_sdram_ctrl : entity work.sdram_ctrl_top
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Generic map
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(
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BL => BL,
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f_sysclk => f_sysclk
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)
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Port map
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(
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sys_rst_in => RST_I,
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sys_clk0_in => CLK_I,
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sys_clk270_in => CLK270_I,
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capture_clk270_in => CLK270VAR_I,
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-- User interface
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u_data_vld => u_data_vld,
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u_data_req_w => u_req_wr,
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u_data_req_r => open,
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u_tag_in => u_tag_in,
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u_tag_rd => u_tag_rd,
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u_tag_wr => u_tag_wr,
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u_busy => u_busy,
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u_addr => u_addr,
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u_cmd => u_cmd,
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u_cmd_we => u_cmd_we,
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u_data_wr => u_data_w,
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u_data_rd => u_data_r,
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u_dm => u_dm_wr_in,
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-- SDRAM signals
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sd_clk_p => sd_clk_p,
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sd_clk_n => sd_clk_n,
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sd_cke => sd_cke,
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sd_cs_n => sd_cs_n,
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sd_cas_n => sd_cas_n,
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sd_ras_n => sd_ras_n,
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sd_we_n => sd_we_n,
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sd_addr => sd_addr,
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sd_ba => sd_ba,
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sd_dm => sd_dm,
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sd_dqs => sd_dqs,
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sd_data => sd_data
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);
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------------------------------------------------------------------------------------------
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SRDY_O <= rdy;
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ACK_O <= not (read_fifo_empty);
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DAT_O <= read_fifo_data_out;
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rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
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write_fifo_we <= STB_I and WE_I and rdy;
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write_fifo_data_in <= DAT_I;
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write_fifo_dm_in <= not SEL_I;
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cat_fifo_we <= STB_I and rdy;
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cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ;
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addr_fifo_in <= ADDR_I(25 downto 3) & "0";
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tag_fifo_in <= "000" & ADDR_I(2);
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u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
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u_cmd <= cmd_fifo_out;
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u_addr <= addr_fifo_out;
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u_dm_wr_in <= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when u_tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
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u_tag_in <= tag_fifo_out;
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u_data_w <= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when u_tag_wr(0) = '1' else write_fifo_data_out(63 downto 0);
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write_fifo_re <= u_req_wr and (not write_fifo_empty);
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cat_fifo_re <= u_cmd_we;
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read_fifo_re <= (not read_fifo_empty) and MRDY_I;
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read_fifo_we <= u_data_vld;
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read_fifo_data_in <= (u_data_r(31 downto 0) & u_data_r(63 downto 32)) when u_tag_rd(0) = '1' else u_data_r(63 downto 0);
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end architecture struct;
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@@ -0,0 +1,860 @@
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-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.fifo_ctrl_pkg.all;
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
|
||||
entity tb_sdram_ctrl_frontend64_wb is
|
||||
end;
|
||||
|
||||
architecture struct of tb_sdram_ctrl_frontend64_wb is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BURST_LEN : natural := 2;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '1';
|
||||
signal locked : std_logic;
|
||||
signal error : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
signal clk_fb : std_logic;
|
||||
signal part_clk_p : std_logic;
|
||||
signal part_clk_n : std_logic;
|
||||
signal part_cke : std_logic;
|
||||
signal part_cs_n : std_logic;
|
||||
signal part_we_n : std_logic;
|
||||
signal part_ras_n : std_logic;
|
||||
signal part_cas_n : std_logic;
|
||||
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal CLK_O : std_logic;
|
||||
signal CLK270_O : std_logic;
|
||||
signal CLK270VAR_O : std_logic;
|
||||
signal RST_O : std_logic;
|
||||
signal CYC_O : std_logic := '0';
|
||||
signal STB_O : std_logic := '0';
|
||||
signal WE_O : std_logic := '0';
|
||||
signal SEL_O : unsigned(SDR_DM_WIDTH-1 downto 0);
|
||||
signal ACK_I : std_logic;
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic;
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal DAT_I : unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
signal DAT_O : unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
|
||||
signal dout_rst : std_logic := '0';
|
||||
signal dout_reg : unsigned(31 downto 0);
|
||||
signal dout_cnt : natural range 0 to 255;
|
||||
|
||||
signal sddat : unsigned(31 downto 0) := (others => '-');
|
||||
signal sdsel : unsigned(3 downto 0) := (others => '1');
|
||||
|
||||
type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
|
||||
signal sd_cmd : sd_cmd_t;
|
||||
|
||||
begin
|
||||
|
||||
process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
|
||||
variable cmd : unsigned (2 downto 0);
|
||||
|
||||
begin
|
||||
cmd := part_ras_n & part_cas_n & part_we_n;
|
||||
sd_cmd <= nop;
|
||||
if part_cs_n = '0' then
|
||||
case cmd is
|
||||
when "000" =>
|
||||
sd_cmd <= lmr;
|
||||
when "001" =>
|
||||
sd_cmd <= ar;
|
||||
when "010" =>
|
||||
sd_cmd <= pre;
|
||||
when "011" =>
|
||||
sd_cmd <= act;
|
||||
when "100" =>
|
||||
sd_cmd <= write;
|
||||
when "101" =>
|
||||
sd_cmd <= read;
|
||||
when "110" =>
|
||||
sd_cmd <= bst;
|
||||
when "111" =>
|
||||
sd_cmd <= nop;
|
||||
|
||||
when others =>
|
||||
sd_cmd <= nop;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_clockgen : entity work.clockgen
|
||||
GENERIC MAP
|
||||
(
|
||||
sys1_phaseshift => 0,
|
||||
frequency_hz => 100E6
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- Clocks and Reset
|
||||
rst => rst, -- external async reset, low active
|
||||
clk_in => clk, -- system clock (e.g. 100MHz), from board
|
||||
clk_fb_in => clk_fb, -- feedback clock
|
||||
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
|
||||
sys1_clk270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
|
||||
sys0_clk0_out => CLK_O, -- System clock #0, dcm#0 output 0°
|
||||
sys0_clk270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
|
||||
locked_out => locked, -- DCM locked status
|
||||
error_out => error
|
||||
);
|
||||
|
||||
|
||||
clk_fb <= part_clk_p after 1 ns;
|
||||
RST_O <= not locked;
|
||||
DAT_O <= X"DEADBEEF" & sddat;
|
||||
SEL_O <= "0000" & sdsel;
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
|
||||
GENERIC MAP
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
f_sysclk => 100E6,
|
||||
fifo_depth => 3
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
RST_I => RST_O,
|
||||
CLK_I => CLK_O,
|
||||
CLK270_I => CLK270_O,
|
||||
CLK270VAR_I => CLK270VAR_O,
|
||||
|
||||
CYC_I => CYC_O,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_I,
|
||||
SRDY_O => SRDY_I,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_I,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => part_clk_p,
|
||||
sd_clk_n => part_clk_n,
|
||||
sd_cke => part_cke,
|
||||
sd_cs_n => part_cs_n,
|
||||
sd_cas_n => part_cas_n,
|
||||
sd_ras_n => part_ras_n,
|
||||
sd_we_n => part_we_n,
|
||||
sd_addr => part_addr,
|
||||
sd_ba => part_ba,
|
||||
sd_dm => part_dm,
|
||||
sd_dqs => part_dqs,
|
||||
sd_data => part_data
|
||||
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map
|
||||
(
|
||||
dq => std_logic_vector(part_data(15 downto 0)),
|
||||
dqs => std_logic_vector(part_dqs(1 downto 0)),
|
||||
addr => std_logic_vector(part_addr),
|
||||
ba => std_logic_vector(part_ba),
|
||||
clk => part_clk_p,
|
||||
clk_n => part_clk_n,
|
||||
cke => part_cke,
|
||||
cs_n => part_cs_n,
|
||||
ras_n => part_ras_n,
|
||||
cas_n => part_cas_n,
|
||||
we_n => part_we_n,
|
||||
dm => std_logic_vector(part_dm(1 downto 0))
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_1 : entity work.mt46v16m16
|
||||
port map
|
||||
(
|
||||
dq => std_logic_vector(part_data(31 downto 16)),
|
||||
dqs => std_logic_vector(part_dqs(3 downto 2)),
|
||||
addr => std_logic_vector(part_addr),
|
||||
ba => std_logic_vector(part_ba),
|
||||
clk => part_clk_p,
|
||||
clk_n => part_clk_n,
|
||||
cke => part_cke,
|
||||
cs_n => part_cs_n,
|
||||
ras_n => part_ras_n,
|
||||
cas_n => part_cas_n,
|
||||
we_n => part_we_n,
|
||||
dm => std_logic_vector(part_dm(3 downto 2))
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
read_register:
|
||||
process(CLK_O)
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if dout_rst = '1' then
|
||||
dout_cnt <= 0;
|
||||
elsif ACK_I = '1' and WE_O = '0' then
|
||||
dout_reg <= DAT_I(31 downto 0);
|
||||
dout_cnt <= dout_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
|
||||
wait until RST_O = '0';
|
||||
-- 8 single cycles
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sddat <= X"1234_0000";
|
||||
ADDR_O <= X"0000_0000";
|
||||
|
||||
for i in 0 to 8192 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
sddat <= sddat + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0000";
|
||||
|
||||
for i in 0 to 31 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 31;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
-- 1-word burst cycle
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sdsel <= "0011";
|
||||
ADDR_O <= X"0000_0080";
|
||||
sddat <= X"DEADBEEF";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
-- 1-word burst cycle
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0080";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and ACK_I = '1';
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0000";
|
||||
|
||||
for i in 0 to 31 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 31;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sdsel <= "1111";
|
||||
sddat <= X"1111_0000";
|
||||
ADDR_O <= X"0000_0000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
sddat <= sddat + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sdsel <= "1111";
|
||||
sddat <= X"2222_0000";
|
||||
ADDR_O <= X"0000_0400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
sddat <= sddat + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sdsel <= "1111";
|
||||
sddat <= X"3333_0000";
|
||||
ADDR_O <= X"0000_0800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
sddat <= sddat + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sdsel <= "1111";
|
||||
sddat <= X"4444_0000";
|
||||
ADDR_O <= X"0000_0C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
sddat <= sddat + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sdsel <= "1111";
|
||||
sddat <= X"1111_0000";
|
||||
ADDR_O <= X"0000_1000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
sddat <= sddat + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sdsel <= "1111";
|
||||
sddat <= X"2222_0000";
|
||||
ADDR_O <= X"0000_1400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
sddat <= sddat + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sdsel <= "1111";
|
||||
sddat <= X"3333_0000";
|
||||
ADDR_O <= X"0000_1800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
sddat <= sddat + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
sdsel <= "1111";
|
||||
sddat <= X"4444_0000";
|
||||
ADDR_O <= X"0000_1C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
sddat <= sddat + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture struct;
|
||||
Reference in New Issue
Block a user