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- pulled out clkgen. vga_clk is now provided from higher level

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git-svn-id: http://moon:8086/svn/vhdl/trunk@583 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-03 20:51:17 +00:00
parent 0c716c1cde
commit 7cdf99b1f5
3 changed files with 30 additions and 51 deletions
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lib/VGA_ctrl/src/vga_frontend64.vhd
+9 -12
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@@ -21,12 +21,12 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.utils_pkg.all;
use work.vga_types.all;
entity vga_frontend64 is
Generic
(
sys_freq : integer := 100E6;
fifo_depth : integer := 2048;
fifo_almost_full_thresh : natural := 2000;
fifo_almost_empty_thresh : natural := 48;
@@ -63,7 +63,8 @@ entity vga_frontend64 is
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_out : out std_logic;
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
@@ -76,9 +77,6 @@ end vga_frontend64;
architecture Behavioral of vga_frontend64 is
signal vga_clk : std_logic;
-- Color FIFO signals
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
@@ -140,13 +138,10 @@ architecture Behavioral of vga_frontend64 is
begin
vga_clk_out <= vga_clk;
inst_vga_backend : entity work.vga_backend
GENERIC MAP
(
sys_freq => sys_freq,
tsvga => tsvga
tsvga => tsvga
)
PORT MAP
(
@@ -175,7 +170,8 @@ inst_vga_backend : entity work.vga_backend
stat_vpos => stat_vpos,
-- VGA domain signals
vga_clk_out => vga_clk,
vga_clk_in => vga_clk_in,
vga_clk_ce => vga_clk_ce,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
@@ -206,7 +202,7 @@ inst_linefifo: entity work.fifo_async
(
rst => RST_I,
clk_w => CLK_I,
clk_r => vga_clk,
clk_r => vga_clk_in,
we => fifo_color_we,
re => fifo_color_re,
data_w => fifo_color_in,
@@ -364,7 +360,7 @@ inst_char_gen : entity work.char_gen
(
rst => RST_I,
sys_clk => CLK_I,
vga_clk => vga_clk,
vga_clk => vga_clk_in,
ce => cg_en,
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,
@@ -380,6 +376,7 @@ inst_char_gen : entity work.char_gen
);
SRDY_O <= CYC_I; -- and cg_rdy;
SDAT_O <= X"0000000" & "000" & cg_rdy;
MDAT_O <= (others => '-');
scan_rdy <= stat_hready and stat_vready;
cg_en <= stat_scan;