diff --git a/lib/VGA_ctrl/src/vga_backend.vhd b/lib/VGA_ctrl/src/vga_backend.vhd index e9ebc99..ed741ec 100644 --- a/lib/VGA_ctrl/src/vga_backend.vhd +++ b/lib/VGA_ctrl/src/vga_backend.vhd @@ -26,8 +26,7 @@ use work.vga_types.all; entity vga_backend is Generic ( - sys_freq : integer := 100E6; - tsvga : vga_timespec_t := ts_vga_800_600_72 + tsvga : vga_timespec_t := ts_vga_800_600_72 ); Port ( @@ -56,7 +55,8 @@ entity vga_backend is stat_vpos : out natural range 0 to tsvga.ts_v.ncyc_scan-1; -- VGA domain signals - vga_clk_out : out std_logic; + vga_clk_in : in std_logic; + vga_clk_ce : in std_logic; vga_red : out unsigned(7 downto 0); vga_green : out unsigned(7 downto 0); vga_blue : out unsigned(7 downto 0); @@ -77,28 +77,10 @@ architecture Behavioral of vga_backend is signal vsync : std_logic; signal hready : std_logic; signal vready : std_logic; - signal vga_clk : std_logic; - signal dcm_locked : std_logic; signal rst : std_logic; begin - vga_clk_out <= vga_clk; - -inst_clkgen: entity work.clkgen - GENERIC MAP - ( - sys_freq => sys_freq, - tsvga => tsvga - ) - PORT MAP - ( - rst => sys_rst, - clk => sys_clk, - vga_clk => vga_clk, - dcm_locked => dcm_locked - ); - inst_vga_timing: entity work.vga_timing GENERIC MAP ( @@ -107,8 +89,8 @@ inst_vga_timing: entity work.vga_timing PORT MAP ( sys_rst => sys_rst, - vga_clk => vga_clk, - vga_ce => dcm_locked, + vga_clk => vga_clk_in, + vga_ce => vga_clk_ce, sync_h => hsync, sync_v => vsync, scan_pos_h => stat_hpos, @@ -120,8 +102,8 @@ inst_vga_timing: entity work.vga_timing ); --------------------------------------------------------------------------------------------- - rst <= not dcm_locked; - stat_vga_rdy <= dcm_locked; + rst <= not vga_clk_ce; + stat_vga_rdy <= vga_clk_ce; stat_hsync <= hsync; stat_vsync <= vsync; stat_hscan <= is_hscan; @@ -136,11 +118,11 @@ inst_vga_timing: entity work.vga_timing --------------------------------------------------------------------------------------------- proc_vga_start: - process (rst, vga_clk) + process (rst, vga_clk_in) begin if rst = '1' then scan_enable <= '0'; - elsif rising_edge(vga_clk) then + elsif rising_edge(vga_clk_in) then if vsync = '1' then if ctrl_scan_en = '1' then scan_enable <= '1'; @@ -152,11 +134,11 @@ inst_vga_timing: entity work.vga_timing end process; proc_vga_color_out: - process (vga_clk) + process (vga_clk_in) variable do_scan : std_logic; variable color : color_t; begin - if rising_edge(vga_clk) then + if rising_edge(vga_clk_in) then vga_red <= X"00"; vga_green <= X"00"; vga_blue <= X"00"; @@ -175,7 +157,7 @@ inst_vga_timing: entity work.vga_timing --------------------------------------------------------------------------------------------- proc_vga_sync_out: - process (rst, vga_clk) + process (rst, vga_clk_in) variable hsync_r : std_logic; variable vsync_r : std_logic; begin @@ -184,7 +166,7 @@ inst_vga_timing: entity work.vga_timing vga_vsync <= tsvga.ts_v.sync_polarity; hsync_r := tsvga.ts_h.sync_polarity; vsync_r := tsvga.ts_v.sync_polarity; - elsif rising_edge(vga_clk) then + elsif rising_edge(vga_clk_in) then vga_hsync <= hsync_r; vga_vsync <= vsync_r; hsync_r := hsync xor (not tsvga.ts_h.sync_polarity); diff --git a/lib/VGA_ctrl/src/vga_frontend.vhd b/lib/VGA_ctrl/src/vga_frontend.vhd index 78eae44..56d086a 100644 --- a/lib/VGA_ctrl/src/vga_frontend.vhd +++ b/lib/VGA_ctrl/src/vga_frontend.vhd @@ -21,12 +21,12 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; +use work.utils_pkg.all; use work.vga_types.all; entity vga_frontend is Generic ( - sys_freq : integer := 100E6; fifo_depth : integer := 2048; fifo_almost_full_thresh : natural := 2000; fifo_almost_empty_thresh : natural := 48; @@ -63,7 +63,8 @@ entity vga_frontend is SDAT_O : out unsigned(31 downto 0); -- VGA signals - vga_clk_out : out std_logic; + vga_clk_in : in std_logic; + vga_clk_ce : in std_logic; vga_red : out unsigned(7 downto 0); vga_green : out unsigned(7 downto 0); vga_blue : out unsigned(7 downto 0); @@ -135,12 +136,9 @@ architecture Behavioral of vga_frontend is begin - vga_clk_out <= vga_clk; - inst_vga_backend : entity work.vga_backend GENERIC MAP ( - sys_freq => sys_freq, tsvga => tsvga ) PORT MAP @@ -170,7 +168,8 @@ inst_vga_backend : entity work.vga_backend stat_vpos => stat_vpos, -- VGA domain signals - vga_clk_out => vga_clk, + vga_clk_in => vga_clk_in, + vga_clk_ce => vga_clk_ce, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, @@ -200,7 +199,7 @@ inst_linefifo: entity work.fifo_async ( rst => RST_I, clk_w => CLK_I, - clk_r => vga_clk, + clk_r => vga_clk_in, we => fifo_color_we, re => fifo_color_re, data_w => fifo_color_in, @@ -356,7 +355,7 @@ inst_char_gen : entity work.char_gen ( rst => RST_I, sys_clk => CLK_I, - vga_clk => vga_clk, + vga_clk => vga_clk_in, ce => cg_en, frame_pulse => scan_rdy, clr_screen => cg_clr_screen, @@ -378,6 +377,7 @@ inst_char_gen : entity work.char_gen cg_clr_screen <= ADDR_I(5) and CYC_I and STB_I and WE_I; cg_clr_line <= ADDR_I(6) and CYC_I and STB_I and WE_I; SDAT_O <= X"0000000" & "000" & cg_rdy; + MDAT_O <= (others => '-'); scan_rdy <= stat_hready and stat_vready; cg_en <= stat_scan; diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd index 020899c..b2123f2 100644 --- a/lib/VGA_ctrl/src/vga_frontend64.vhd +++ b/lib/VGA_ctrl/src/vga_frontend64.vhd @@ -21,12 +21,12 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; +use work.utils_pkg.all; use work.vga_types.all; entity vga_frontend64 is Generic ( - sys_freq : integer := 100E6; fifo_depth : integer := 2048; fifo_almost_full_thresh : natural := 2000; fifo_almost_empty_thresh : natural := 48; @@ -63,7 +63,8 @@ entity vga_frontend64 is SDAT_O : out unsigned(31 downto 0); -- VGA signals - vga_clk_out : out std_logic; + vga_clk_in : in std_logic; + vga_clk_ce : in std_logic; vga_red : out unsigned(7 downto 0); vga_green : out unsigned(7 downto 0); vga_blue : out unsigned(7 downto 0); @@ -76,9 +77,6 @@ end vga_frontend64; architecture Behavioral of vga_frontend64 is - - signal vga_clk : std_logic; - -- Color FIFO signals signal fifo_full : std_logic; signal fifo_empty : std_logic; @@ -140,13 +138,10 @@ architecture Behavioral of vga_frontend64 is begin - vga_clk_out <= vga_clk; - inst_vga_backend : entity work.vga_backend GENERIC MAP ( - sys_freq => sys_freq, - tsvga => tsvga + tsvga => tsvga ) PORT MAP ( @@ -175,7 +170,8 @@ inst_vga_backend : entity work.vga_backend stat_vpos => stat_vpos, -- VGA domain signals - vga_clk_out => vga_clk, + vga_clk_in => vga_clk_in, + vga_clk_ce => vga_clk_ce, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, @@ -206,7 +202,7 @@ inst_linefifo: entity work.fifo_async ( rst => RST_I, clk_w => CLK_I, - clk_r => vga_clk, + clk_r => vga_clk_in, we => fifo_color_we, re => fifo_color_re, data_w => fifo_color_in, @@ -364,7 +360,7 @@ inst_char_gen : entity work.char_gen ( rst => RST_I, sys_clk => CLK_I, - vga_clk => vga_clk, + vga_clk => vga_clk_in, ce => cg_en, frame_pulse => scan_rdy, clr_screen => cg_clr_screen, @@ -380,6 +376,7 @@ inst_char_gen : entity work.char_gen ); SRDY_O <= CYC_I; -- and cg_rdy; SDAT_O <= X"0000000" & "000" & cg_rdy; + MDAT_O <= (others => '-'); scan_rdy <= stat_hready and stat_vready; cg_en <= stat_scan;