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- pulled out clkgen. vga_clk is now provided from higher level

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git-svn-id: http://moon:8086/svn/vhdl/trunk@583 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-03 20:51:17 +00:00
parent 0c716c1cde
commit 7cdf99b1f5
3 changed files with 30 additions and 51 deletions
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lib/VGA_ctrl/src/vga_backend.vhd
+13 -31
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@@ -26,8 +26,7 @@ use work.vga_types.all;
entity vga_backend is
Generic
(
sys_freq : integer := 100E6;
tsvga : vga_timespec_t := ts_vga_800_600_72
tsvga : vga_timespec_t := ts_vga_800_600_72
);
Port
(
@@ -56,7 +55,8 @@ entity vga_backend is
stat_vpos : out natural range 0 to tsvga.ts_v.ncyc_scan-1;
-- VGA domain signals
vga_clk_out : out std_logic;
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
@@ -77,28 +77,10 @@ architecture Behavioral of vga_backend is
signal vsync : std_logic;
signal hready : std_logic;
signal vready : std_logic;
signal vga_clk : std_logic;
signal dcm_locked : std_logic;
signal rst : std_logic;
begin
vga_clk_out <= vga_clk;
inst_clkgen: entity work.clkgen
GENERIC MAP
(
sys_freq => sys_freq,
tsvga => tsvga
)
PORT MAP
(
rst => sys_rst,
clk => sys_clk,
vga_clk => vga_clk,
dcm_locked => dcm_locked
);
inst_vga_timing: entity work.vga_timing
GENERIC MAP
(
@@ -107,8 +89,8 @@ inst_vga_timing: entity work.vga_timing
PORT MAP
(
sys_rst => sys_rst,
vga_clk => vga_clk,
vga_ce => dcm_locked,
vga_clk => vga_clk_in,
vga_ce => vga_clk_ce,
sync_h => hsync,
sync_v => vsync,
scan_pos_h => stat_hpos,
@@ -120,8 +102,8 @@ inst_vga_timing: entity work.vga_timing
);
---------------------------------------------------------------------------------------------
rst <= not dcm_locked;
stat_vga_rdy <= dcm_locked;
rst <= not vga_clk_ce;
stat_vga_rdy <= vga_clk_ce;
stat_hsync <= hsync;
stat_vsync <= vsync;
stat_hscan <= is_hscan;
@@ -136,11 +118,11 @@ inst_vga_timing: entity work.vga_timing
---------------------------------------------------------------------------------------------
proc_vga_start:
process (rst, vga_clk)
process (rst, vga_clk_in)
begin
if rst = '1' then
scan_enable <= '0';
elsif rising_edge(vga_clk) then
elsif rising_edge(vga_clk_in) then
if vsync = '1' then
if ctrl_scan_en = '1' then
scan_enable <= '1';
@@ -152,11 +134,11 @@ inst_vga_timing: entity work.vga_timing
end process;
proc_vga_color_out:
process (vga_clk)
process (vga_clk_in)
variable do_scan : std_logic;
variable color : color_t;
begin
if rising_edge(vga_clk) then
if rising_edge(vga_clk_in) then
vga_red <= X"00";
vga_green <= X"00";
vga_blue <= X"00";
@@ -175,7 +157,7 @@ inst_vga_timing: entity work.vga_timing
---------------------------------------------------------------------------------------------
proc_vga_sync_out:
process (rst, vga_clk)
process (rst, vga_clk_in)
variable hsync_r : std_logic;
variable vsync_r : std_logic;
begin
@@ -184,7 +166,7 @@ inst_vga_timing: entity work.vga_timing
vga_vsync <= tsvga.ts_v.sync_polarity;
hsync_r := tsvga.ts_h.sync_polarity;
vsync_r := tsvga.ts_v.sync_polarity;
elsif rising_edge(vga_clk) then
elsif rising_edge(vga_clk_in) then
vga_hsync <= hsync_r;
vga_vsync <= vsync_r;
hsync_r := hsync xor (not tsvga.ts_h.sync_polarity);