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- FIFOs only use registered output DPRAMs

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git-svn-id: http://moon:8086/svn/vhdl/trunk@944 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-02-09 10:42:07 +00:00
parent 61d9104fb2
commit 7b972d0084
6 changed files with 35 additions and 34 deletions
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lib/FIFO/sim/tb_fifo_async.fdo
+1 -1
View File
@@ -3,7 +3,7 @@
vlib work
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../src/gray_counter.vhd"
vcom -explicit -93 "../src/dpram_1w1r.vhd"
vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
vcom -explicit -93 "../src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../src/fifo_async.vhd"
vcom -explicit -93 "../src/tb_fifo_async.vhd"
lib/FIFO/sim/tb_fifo_sync.fdo
+1 -1
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@@ -2,7 +2,7 @@
##
vlib work
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../src/dpram_1w1r.vhd"
vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
vcom -explicit -93 "../src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../src/fifo_sync.vhd"
vcom -explicit -93 "../src/tb_fifo_sync.vhd"
lib/FIFO/src/fifo_async.vhd
+10 -10
View File
@@ -31,13 +31,13 @@ use work.fifo_ctrl_pkg.all;
entity fifo_async is
Generic
(
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4;
allow_full_writes : boolean := false;
allow_empty_reads : boolean := false;
do_last_read_update : boolean := true
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4;
allow_full_writes : boolean := false;
allow_empty_reads : boolean := false;
do_last_read_update : boolean := true
);
Port
(
@@ -102,15 +102,15 @@ begin
);
inst_dpram_1w1r: entity work.dpram_1w1r
inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ro
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP(
clka => clk_w,
clkb => clk_r,
clk_a => clk_w,
clk_b => clk_r,
en_a => '1',
en_b => mem_rd_en,
we_a => mem_wr_en,
lib/FIFO/src/fifo_sync.vhd
+11 -11
View File
@@ -31,13 +31,13 @@ use work.fifo_ctrl_pkg.all;
entity fifo_sync is
Generic
(
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4;
allow_full_writes : boolean := false;
allow_empty_reads : boolean := false;
do_last_read_update : boolean := true
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4;
allow_full_writes : boolean := false;
allow_empty_reads : boolean := false;
do_last_read_update : boolean := true
);
Port
@@ -101,15 +101,15 @@ inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
);
inst_dpram_1w1r: entity work.dpram_1w1r
inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ro
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP(
clka => clk,
clkb => clk,
clk_a => clk,
clk_b => clk,
en_a => '1',
en_b => mem_rd_en,
we_a => mem_wr_en,
@@ -118,6 +118,6 @@ inst_dpram_1w1r: entity work.dpram_1w1r
din_a => data_w,
dout_b => data_r
);
end Behavioral;
lib/FIFO/src/tb_fifo_async.vhd
+7 -7
View File
@@ -68,13 +68,13 @@ BEGIN
uut: entity work.fifo_async
GENERIC MAP
(
addr_width => ADDR_WIDTH,
data_width => DATA_WIDTH,
almost_full_thresh => 6,
almost_empty_thresh => 2,
allow_full_writes => false,
allow_empty_reads => false,
do_last_read_update => false
addr_width => ADDR_WIDTH,
data_width => DATA_WIDTH,
almost_full_thresh => 6,
almost_empty_thresh => 2,
allow_full_writes => false,
allow_empty_reads => false,
do_last_read_update => false
)
PORT MAP
(
lib/FIFO/src/tb_fifo_sync.vhd
+5 -4
View File
@@ -66,10 +66,11 @@ BEGIN
uut: entity work.fifo_sync
GENERIC MAP
(
data_width => DATA_WIDTH,
addr_width => ADDR_WIDTH,
almost_full_thresh => 6,
almost_empty_thresh => 2
data_width => DATA_WIDTH,
addr_width => ADDR_WIDTH,
almost_full_thresh => 6,
almost_empty_thresh => 2,
do_last_read_update => false
)
PORT MAP
(