diff --git a/lib/FIFO/sim/tb_fifo_async.fdo b/lib/FIFO/sim/tb_fifo_async.fdo
index c35254b..c164ab6 100644
--- a/lib/FIFO/sim/tb_fifo_async.fdo
+++ b/lib/FIFO/sim/tb_fifo_async.fdo
@@ -3,7 +3,7 @@
 vlib work
 vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../src/gray_counter.vhd"
-vcom -explicit  -93 "../src/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
 vcom -explicit  -93 "../src/fifo_async_ctrl.vhd"
 vcom -explicit  -93 "../src/fifo_async.vhd"
 vcom -explicit  -93 "../src/tb_fifo_async.vhd"
diff --git a/lib/FIFO/sim/tb_fifo_sync.fdo b/lib/FIFO/sim/tb_fifo_sync.fdo
index 4b01cf4..6922e87 100644
--- a/lib/FIFO/sim/tb_fifo_sync.fdo
+++ b/lib/FIFO/sim/tb_fifo_sync.fdo
@@ -2,7 +2,7 @@
 ##
 vlib work
 vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../src/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
 vcom -explicit  -93 "../src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/tb_fifo_sync.vhd"
diff --git a/lib/FIFO/src/fifo_async.vhd b/lib/FIFO/src/fifo_async.vhd
index cff8591..35340e7 100644
--- a/lib/FIFO/src/fifo_async.vhd
+++ b/lib/FIFO/src/fifo_async.vhd
@@ -31,13 +31,13 @@ use work.fifo_ctrl_pkg.all;
 entity fifo_async is
 	Generic
 	(
-		addr_width			: natural := 4;
-		data_width			: natural := 8;
-		almost_full_thresh	: integer := 12;
-		almost_empty_thresh	: integer := 4;
-		allow_full_writes	: boolean := false;
-		allow_empty_reads	: boolean := false;
-		do_last_read_update	: boolean := true
+		addr_width					: natural := 4;
+		data_width					: natural := 8;
+		almost_full_thresh			: integer := 12;
+		almost_empty_thresh			: integer := 4;
+		allow_full_writes			: boolean := false;
+		allow_empty_reads			: boolean := false;
+		do_last_read_update			: boolean := true
 	);
 	Port
 	(
@@ -102,15 +102,15 @@ begin
 
 	);
 
-inst_dpram_1w1r: entity work.dpram_1w1r
+inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ro
 	GENERIC MAP
 	(
 		addr_width	=> addr_width,
 		data_width	=> data_width
 	)
 	PORT MAP(
-		clka		=> clk_w,
-		clkb		=> clk_r,
+		clk_a		=> clk_w,
+		clk_b		=> clk_r,
 		en_a		=> '1',
 		en_b		=> mem_rd_en,
 		we_a		=> mem_wr_en,
diff --git a/lib/FIFO/src/fifo_sync.vhd b/lib/FIFO/src/fifo_sync.vhd
index 6be9075..5c8d8c8 100644
--- a/lib/FIFO/src/fifo_sync.vhd
+++ b/lib/FIFO/src/fifo_sync.vhd
@@ -31,13 +31,13 @@ use work.fifo_ctrl_pkg.all;
 entity fifo_sync is
 	Generic 
 	(
-		addr_width			: natural := 4;
-		data_width			: natural := 8;
-		almost_full_thresh	: integer := 12;
-		almost_empty_thresh	: integer := 4;
-		allow_full_writes	: boolean := false;
-		allow_empty_reads	: boolean := false;
-		do_last_read_update	: boolean := true
+		addr_width					: natural := 4;
+		data_width					: natural := 8;
+		almost_full_thresh			: integer := 12;
+		almost_empty_thresh			: integer := 4;
+		allow_full_writes			: boolean := false;
+		allow_empty_reads			: boolean := false;
+		do_last_read_update			: boolean := true
 		
 	);
 	Port
@@ -101,15 +101,15 @@ inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
 
 	);
 
-inst_dpram_1w1r: entity work.dpram_1w1r
+inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ro
 	GENERIC MAP
 	(
 		addr_width	=> addr_width,
 		data_width	=> data_width
 	)
 	PORT MAP(
-		clka		=> clk,
-		clkb		=> clk,
+		clk_a		=> clk,
+		clk_b		=> clk,
 		en_a		=> '1',
 		en_b		=> mem_rd_en,
 		we_a		=> mem_wr_en,
@@ -118,6 +118,6 @@ inst_dpram_1w1r: entity work.dpram_1w1r
 		din_a		=> data_w,
 		dout_b		=> data_r
 	);
-	
+
 end Behavioral;
 
diff --git a/lib/FIFO/src/tb_fifo_async.vhd b/lib/FIFO/src/tb_fifo_async.vhd
index c285ec7..31e6b36 100644
--- a/lib/FIFO/src/tb_fifo_async.vhd
+++ b/lib/FIFO/src/tb_fifo_async.vhd
@@ -68,13 +68,13 @@ BEGIN
 	uut: entity work.fifo_async
 	GENERIC MAP
 	(
-		addr_width			=> ADDR_WIDTH,
-		data_width			=> DATA_WIDTH,
-		almost_full_thresh	=> 6,
-		almost_empty_thresh	=> 2,
-		allow_full_writes	=> false,
-		allow_empty_reads	=> false,
-		do_last_read_update	=> false
+		addr_width					=> ADDR_WIDTH,
+		data_width					=> DATA_WIDTH,
+		almost_full_thresh			=> 6,
+		almost_empty_thresh			=> 2,
+		allow_full_writes			=> false,
+		allow_empty_reads			=> false,
+		do_last_read_update			=> false
 	)
 	PORT MAP
 	(
diff --git a/lib/FIFO/src/tb_fifo_sync.vhd b/lib/FIFO/src/tb_fifo_sync.vhd
index c25b260..f7fb6a5 100644
--- a/lib/FIFO/src/tb_fifo_sync.vhd
+++ b/lib/FIFO/src/tb_fifo_sync.vhd
@@ -66,10 +66,11 @@ BEGIN
 	uut: entity work.fifo_sync
 	GENERIC MAP
 	(
-		data_width			=> DATA_WIDTH,
-		addr_width			=> ADDR_WIDTH,
-		almost_full_thresh	=> 6,
-		almost_empty_thresh	=> 2
+		data_width					=> DATA_WIDTH,
+		addr_width					=> ADDR_WIDTH,
+		almost_full_thresh			=> 6,
+		almost_empty_thresh			=> 2,
+		do_last_read_update			=> false
 	)
 	PORT MAP
 	(