jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added libs

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1101 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-16 19:17:38 +00:00
parent 7ac9bde7ff
commit 7705d1220e
1 changed files with 2 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/sim/modelsim.ini
+2
View File
@@ -12,6 +12,8 @@ others = $MODEL_TECH/../modelsim.ini
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
unisim = W:/SVN/vhdl/trunk/Common/sim/unisim
altera = W:/SVN/vhdl/trunk/Common/sim/altera/lib/altera
cycloneive = W:/SVN/vhdl/trunk/Common/sim/altera/lib/cycloneive
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.