diff --git a/lib/CPUs/MIPS/sim/modelsim.ini b/lib/CPUs/MIPS/sim/modelsim.ini
index bb852ba..c95ab97 100644
--- a/lib/CPUs/MIPS/sim/modelsim.ini
+++ b/lib/CPUs/MIPS/sim/modelsim.ini
@@ -12,6 +12,8 @@ others = $MODEL_TECH/../modelsim.ini
 ;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
 
 unisim = W:/SVN/vhdl/trunk/Common/sim/unisim
+altera = W:/SVN/vhdl/trunk/Common/sim/altera/lib/altera
+cycloneive = W:/SVN/vhdl/trunk/Common/sim/altera/lib/cycloneive
 [vcom]
 ; VHDL93 variable selects language version as the default. 
 ; Default is VHDL-2002.