- cleaned up
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@881 cc03376c-175c-47c8-b038-4cd826a8556b
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+5
-286
@@ -26,52 +26,16 @@ LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY tb_emac_jb IS
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END tb_emac_jb;
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ENTITY tb_serdes IS
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END tb_serdes;
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ARCHITECTURE behavior OF tb_emac_jb IS
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ARCHITECTURE behavior OF tb_serdes IS
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constant CLK_PERIOD : time := 10 ns;
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constant MII_CLK_PERIOD : time := 8 ns;
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signal CLK : std_logic := '1';
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signal RST : std_logic := '1';
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-- Slave
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signal CYC_I : std_logic := '0';
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signal STB_I : std_logic := '0';
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signal WE_I : std_logic := '0';
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signal SEL_I : unsigned(3 downto 0);
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signal ACK_O : std_logic;
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signal INT_O : std_logic;
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signal MRDY_I : std_logic;
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signal SRDY_O : std_logic;
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signal ADDR_I : unsigned(31 downto 0) := (others => '-');
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signal DAT_I : unsigned(31 downto 0) := (others => '-');
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signal DAT_O : unsigned(31 downto 0) := (others => '-');
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signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
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-- MII signals
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signal mii_rx_clk_board : std_logic := '1';
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signal mii_tx_clk_board : std_logic := '1';
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signal mii_rx_clk : std_logic := '1';
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signal mii_tx_clk : std_logic := '1';
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signal mii_rx : unsigned(7 downto 0) := (others => '-');
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signal mii_tx : unsigned(7 downto 0);
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signal mii_rx_dv : std_logic := '0';
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signal mii_rx_er : std_logic := '0';
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signal mii_tx_en : std_logic;
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signal mii_tx_er : std_logic;
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signal mii_crs : std_logic := '0';
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signal mii_col : std_logic := '0';
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signal mii_gtx_clk : std_logic;
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signal shift_sa : integer := 0;
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signal shift_din_vld : std_logic := '0';
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signal shift_din : unsigned(31 downto 0) := (others => '-');
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signal shift_dout_vld : std_logic;
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signal shift_dout : unsigned(31 downto 0);
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signal piso_din_vld : std_logic := '0';
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signal piso_din_rdy : std_logic;
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signal piso_din_be : unsigned(3 downto 0) := (others => '0');
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@@ -106,65 +70,9 @@ ARCHITECTURE behavior OF tb_emac_jb IS
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signal sipo2_dout_be : unsigned(1 downto 0);
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signal sipo2_dout : unsigned(7 downto 0);
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type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_read);
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signal emac_action : emac_action_t;
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BEGIN
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inst_emac_jb : entity work.emac_jb
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GENERIC MAP
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(
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f_sysclk => 100.0,
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TX_RAM_SIZE => 2048
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)
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PORT MAP
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(
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CLK_I => CLK,
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RST_I => RST,
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INT_O => INT_O,
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CYC_I => CYC_I,
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STB_I => STB_I,
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SEL_I => SEL_I,
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WE_I => WE_I,
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ACK_O => ACK_O,
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SRDY_O => SRDY_O,
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MRDY_I => MRDY_I,
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ADDR_I => ADDR_I,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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mii_rx_clk => mii_rx_clk_board,
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mii_rx_dv => mii_rx_dv,
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mii_rx_er => mii_rx_er,
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mii_rx => mii_rx,
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mii_tx_clk => mii_tx_clk_board,
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mii_tx_en => mii_tx_en,
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mii_tx_er => mii_tx_er,
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mii_tx => mii_tx,
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mii_gtx_clk => mii_gtx_clk,
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mii_crs => mii_crs,
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mii_col => mii_col
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);
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inst_shifter : entity work.shifter
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GENERIC MAP
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(
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data_width => 32,
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aggregate_size => 4,
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do_pipelined => true
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)
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PORT MAP
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(
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rst => RST,
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clk => CLK,
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sa => shift_sa,
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din_vld => shift_din_vld,
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din => shift_din,
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dout_vld => shift_dout_vld,
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dout => shift_dout
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);
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inst_piso : entity work.piso
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GENERIC MAP
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(
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@@ -186,7 +94,7 @@ inst_piso : entity work.piso
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);
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piso_dout_en <= '0'; --piso2_din_rdy;
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piso_dout_en <= piso2_din_rdy;
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inst_piso2 : entity work.piso
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GENERIC MAP
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@@ -269,206 +177,17 @@ CLK_GEN: process
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CLK <= not CLK;
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end process;
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MII_CLK_GEN: process
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begin
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wait for MII_CLK_PERIOD/2;
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mii_rx_clk <= not mii_rx_clk;
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mii_tx_clk <= not mii_tx_clk;
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end process;
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mii_rx_clk_board <= mii_rx_clk;
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mii_tx_clk_board <= mii_tx_clk;
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DAT_O_register:
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process(CLK)
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begin
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if rising_edge(CLK) then
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if ACK_O = '1' then
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DAT_O_reg <= DAT_O;
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end if;
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end if;
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end process;
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-- Master
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STIMULUS: process
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procedure emac_alloc (size : natural) is
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begin
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-- TX-ALLOCATION
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-- set TX-size
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emac_action <= emac_alloc;
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CYC_I <= '1';
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wait until rising_edge(CLK) and SRDY_O = '1';
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DAT_I <= to_unsigned(size, 16) & X"55AA";
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STB_I <= '1';
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WE_I <= '1';
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ADDR_I <= X"0000_0004";
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wait until rising_edge(CLK) and SRDY_O = '1';
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STB_I <= '0';
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-- set alloc request
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CYC_I <= '1';
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wait until rising_edge(CLK) and SRDY_O = '1';
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DAT_I <= X"0001_0000";
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STB_I <= '1';
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WE_I <= '1';
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ADDR_I <= X"0000_0000";
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wait until rising_edge(CLK) and SRDY_O = '1';
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STB_I <= '0';
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WE_I <= '0';
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-- check alloc busy
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check_bsy:
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while (true) loop
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CYC_I <= '1';
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wait until rising_edge(CLK) and SRDY_O = '1';
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STB_I <= '1';
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ADDR_I <= X"0000_0000";
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wait until rising_edge(CLK) and SRDY_O = '1';
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STB_I <= '0';
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wait until rising_edge(CLK) and ACK_O = '1';
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wait until rising_edge(CLK);
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if DAT_O_reg(16) = '0' then
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exit check_bsy;
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end if;
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end loop;
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emac_action <= emac_idle;
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end procedure emac_alloc;
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procedure emac_write (size : natural) is
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variable data : unsigned (7 downto 0);
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variable num_words : natural;
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begin
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-- FILL TX data
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emac_action <= emac_write;
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if (size mod 4) = 0 then
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num_words := size/4;
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else
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num_words := size/4 + 1;
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end if;
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CYC_I <= '1';
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wait until rising_edge(CLK) and SRDY_O = '1';
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data := X"00";
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ADDR_I <= X"0000_0008";
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WE_I <= '1';
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for i in 1 to num_words loop
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STB_I <= '1';
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DAT_I(7 downto 0) <= data;
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data := data + 1;
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DAT_I(15 downto 8) <= data;
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data := data + 1;
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DAT_I(23 downto 16) <= data;
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data := data + 1;
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DAT_I(31 downto 24) <= data;
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data := data + 1;
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wait until rising_edge(CLK) and SRDY_O = '1';
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end loop;
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STB_I <= '0';
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wait until rising_edge(CLK) and SRDY_O = '1';
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emac_action <= emac_idle;
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end procedure emac_write;
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begin
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wait for 6*MII_CLK_PERIOD;
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wait for 600*CLK_PERIOD;
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RST <= '0';
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wait for 60*CLK_PERIOD;
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-- emac_alloc (1536);
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-- emac_write (1536);
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--
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-- emac_alloc (1536);
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-- emac_write (1536);
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--
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-- emac_alloc (1536);
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-- emac_write (1536);
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--
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-- emac_alloc (1536);
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-- emac_write (1536);
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--
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-- emac_alloc (1536);
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-- emac_write (1536);
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--
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-- emac_alloc (1536);
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-- emac_write (1536);
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--
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-- emac_alloc (1536);
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-- emac_write (1536);
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--
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-- emac_alloc (64);
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-- emac_write (64);
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--
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-- emac_alloc (512);
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-- emac_write (512);
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--
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-- emac_alloc (1536);
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-- emac_write (1536);
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--
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-- emac_alloc (65);
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-- emac_write (65);
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--
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-- emac_alloc (66);
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-- emac_write (66);
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--
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-- emac_alloc (67);
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-- emac_write (67);
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--
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-- emac_alloc (512);
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-- emac_write (64);
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--
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-- emac_alloc (128);
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-- emac_write (128);
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-- wait for 4000*CLK_PERIOD;
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--
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-- wait until rising_edge(CLK);
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-- shift_din <= X"12345678";
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-- shift_sa <= 0;
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-- shift_din_vld <= '1';
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa + 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa + 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa + 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa + 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa + 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa + 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa + 1;
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-- wait until rising_edge(CLK);
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--
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-- shift_sa <= 0;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa - 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa - 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa - 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa - 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa - 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa - 1;
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-- wait until rising_edge(CLK);
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-- shift_sa <= shift_sa - 1;
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--
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-- wait until rising_edge(CLK);
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-- shift_din_vld <= '0';
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for i in 1 to 10 loop
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wait until rising_edge(CLK);
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