From 76eb2dfe3268193aab13d6c3d11b357cdc10629a Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 8 Apr 2010 08:41:47 +0000 Subject: [PATCH] - cleaned up Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@881 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/emac/sim/tb_emac_jb.fdo | 14 +- lib/emac/sim/tb_emac_jb.wdo | 189 +++++------------------ lib/emac/src/tb_emac_jb.vhd | 291 +----------------------------------- 3 files changed, 47 insertions(+), 447 deletions(-) diff --git a/lib/emac/sim/tb_emac_jb.fdo b/lib/emac/sim/tb_emac_jb.fdo index 94bcc1f..dc5d8f1 100644 --- a/lib/emac/sim/tb_emac_jb.fdo +++ b/lib/emac/sim/tb_emac_jb.fdo @@ -3,20 +3,12 @@ ## vlib work vcom -explicit -93 "../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../misc/dpram_1w1r.vhd" -vcom -explicit -93 "../../misc/dpram_2w2r.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" vcom -explicit -93 "../src/piso.vhd" vcom -explicit -93 "../src/sipo.vhd" -vcom -explicit -93 "../src/shifter.vhd" -vcom -explicit -93 "../src/emac_jb.vhd" -vcom -explicit -93 "../src/tb_emac_jb.vhd" -vsim -t 1ps -lib work tb_emac_jb +vcom -explicit -93 "../src/tb_serdes.vhd" +vsim -t 1ps -lib work tb_serdes view wave -do {tb_emac_jb.wdo} +do {tb_serdes.wdo} view structure view signals diff --git a/lib/emac/sim/tb_emac_jb.wdo b/lib/emac/sim/tb_emac_jb.wdo index c921768..4a34ebd 100644 --- a/lib/emac/sim/tb_emac_jb.wdo +++ b/lib/emac/sim/tb_emac_jb.wdo @@ -1,158 +1,47 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_emac_jb/clk -add wave -noupdate -format Logic /tb_emac_jb/rst -add wave -noupdate -format Logic /tb_emac_jb/cyc_i -add wave -noupdate -format Logic /tb_emac_jb/stb_i -add wave -noupdate -format Logic /tb_emac_jb/we_i -add wave -noupdate -format Literal /tb_emac_jb/sel_i -add wave -noupdate -format Logic /tb_emac_jb/ack_o -add wave -noupdate -format Logic /tb_emac_jb/int_o -add wave -noupdate -format Logic /tb_emac_jb/mrdy_i -add wave -noupdate -format Logic /tb_emac_jb/srdy_o -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/addr_i -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_o -add wave -noupdate -format Logic /tb_emac_jb/mii_rx_clk -add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_rx -add wave -noupdate -format Logic /tb_emac_jb/mii_rx_dv -add wave -noupdate -format Logic /tb_emac_jb/mii_rx_er -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_tx -add wave -noupdate -format Logic /tb_emac_jb/mii_tx_en -add wave -noupdate -format Logic /tb_emac_jb/mii_tx_er -add wave -noupdate -format Logic /tb_emac_jb/mii_crs -add wave -noupdate -format Logic /tb_emac_jb/mii_col -add wave -noupdate -format Logic /tb_emac_jb/mii_gtx_clk -add wave -noupdate -divider {Ethernet MAC} -add wave -noupdate -format Logic /tb_emac_jb/clk -add wave -noupdate -format Literal /tb_emac_jb/emac_action -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_err -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_en -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_rdy -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en -add wave -noupdate -format Literal -radix unsigned /tb_emac_jb/inst_emac_jb/tx_nwords_free -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_flush_ptr -add wave -noupdate -format Logic /tb_emac_jb/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_size -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_set -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_adv -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_cnt -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_set -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_adv -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_ptr -add wave -noupdate -format Logic /tb_emac_jb/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_base -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_size -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ok -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req_en -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_commit_en -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ack -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_a -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_b -add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/host_tx_s -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_b -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_b -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_b -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_b -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_b -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_a -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_a -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_a -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_a -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_a -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_a -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_set -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_adv -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_ptr -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_set -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_adv -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_cnt -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_rdy -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_en -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_data_vld -add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tag -add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_remain -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_odd -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_remain_en -add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tx_s -add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/piso_din_be -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/piso_din_rdy -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_size -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_we -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_full -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_din -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_empty -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_re -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_dout -add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_tx_size -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/host_data_we -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_data_reg -add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/inter_frame_gap_cnt -add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/inter_frame_gap_rdy -add wave -noupdate -divider Shifter -add wave -noupdate -format Logic /tb_emac_jb/clk -add wave -noupdate -format Literal /tb_emac_jb/shift_sa -add wave -noupdate -format Logic /tb_emac_jb/shift_din_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_din -add wave -noupdate -format Logic /tb_emac_jb/shift_dout_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_dout +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/rst add wave -noupdate -divider PiSo -add wave -noupdate -format Logic /tb_emac_jb/clk -add wave -noupdate -format Logic /tb_emac_jb/piso_din_vld -add wave -noupdate -format Logic /tb_emac_jb/piso_din_rdy -add wave -noupdate -format Literal /tb_emac_jb/piso_din_be -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_din -add wave -noupdate -format Logic /tb_emac_jb/piso_dout_en -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_dout -add wave -noupdate -format Logic /tb_emac_jb/inst_piso/pre_fin -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/din_reg -add wave -noupdate -format Literal /tb_emac_jb/inst_piso/din_be_reg -add wave -noupdate -format Logic /tb_emac_jb/inst_piso/din_vld_reg -add wave -noupdate -format Literal /tb_emac_jb/inst_piso/shift_cnt_pipe -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/shift_pipe -add wave -noupdate -format Literal /tb_emac_jb/inst_piso/vld_pipe -add wave -noupdate -format Logic /tb_emac_jb/piso2_din_vld -add wave -noupdate -format Logic /tb_emac_jb/piso2_din_rdy -add wave -noupdate -format Literal /tb_emac_jb/piso2_din_be -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_din -add wave -noupdate -format Logic /tb_emac_jb/piso2_dout_en -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_dout -add wave -noupdate -format Logic /tb_emac_jb/piso2_enable -add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/pre_fin -add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/rdy -add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/shift_cnt_pipe -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso2/shift_pipe -add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/vld_pipe +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/piso_din_vld +add wave -noupdate -format Logic /tb_serdes/piso_din_rdy +add wave -noupdate -format Literal /tb_serdes/piso_din_be +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_din +add wave -noupdate -format Logic /tb_serdes/piso_dout_vld +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_dout +add wave -noupdate -format Logic /tb_serdes/piso_dout_en add wave -noupdate -divider SiPo -add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/clk -add wave -noupdate -format Logic /tb_emac_jb/sipo_enable -add wave -noupdate -format Logic /tb_emac_jb/sipo_din_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_din -add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_en -add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_vld -add wave -noupdate -format Literal /tb_emac_jb/sipo_dout_be -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_dout -add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/pre_fin -add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/abort -add wave -noupdate -format Literal /tb_emac_jb/inst_sipo/shift_cnt_pipe -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo/shift_pipe -add wave -noupdate -format Logic /tb_emac_jb/sipo2_enable -add wave -noupdate -format Logic /tb_emac_jb/sipo2_rst -add wave -noupdate -format Logic /tb_emac_jb/sipo2_din_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_din -add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_en -add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_vld -add wave -noupdate -format Literal /tb_emac_jb/sipo2_dout_be -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_dout -add wave -noupdate -format Literal /tb_emac_jb/inst_sipo2/shift_cnt_pipe -add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo2/shift_pipe +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/sipo_enable +add wave -noupdate -format Logic /tb_serdes/sipo_rst +add wave -noupdate -format Logic /tb_serdes/sipo_din_vld +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_din +add wave -noupdate -format Logic /tb_serdes/sipo_dout_vld +add wave -noupdate -format Logic /tb_serdes/sipo_dout_en +add wave -noupdate -format Literal /tb_serdes/sipo_dout_be +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_dout +add wave -noupdate -divider PiSo +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/piso2_din_vld +add wave -noupdate -format Logic /tb_serdes/piso2_din_rdy +add wave -noupdate -format Literal /tb_serdes/piso2_din_be +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_din +add wave -noupdate -format Logic /tb_serdes/piso2_dout_vld +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_dout +add wave -noupdate -format Logic /tb_serdes/piso2_dout_en +add wave -noupdate -divider SiPo +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/sipo2_enable +add wave -noupdate -format Logic /tb_serdes/sipo2_rst +add wave -noupdate -format Logic /tb_serdes/sipo2_din_vld +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_din +add wave -noupdate -format Logic /tb_serdes/sipo2_dout_vld +add wave -noupdate -format Logic /tb_serdes/sipo2_dout_en +add wave -noupdate -format Literal /tb_serdes/sipo2_dout_be +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_dout TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {19622640 ps} 0} {{Cursor 2} {121551751 ps} 0} +WaveRestoreCursors {{Cursor 1} {6910000 ps} 0} {{Cursor 2} {121551751 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left diff --git a/lib/emac/src/tb_emac_jb.vhd b/lib/emac/src/tb_emac_jb.vhd index a46a811..1f16310 100644 --- a/lib/emac/src/tb_emac_jb.vhd +++ b/lib/emac/src/tb_emac_jb.vhd @@ -26,52 +26,16 @@ LIBRARY ieee; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; -ENTITY tb_emac_jb IS -END tb_emac_jb; +ENTITY tb_serdes IS +END tb_serdes; -ARCHITECTURE behavior OF tb_emac_jb IS +ARCHITECTURE behavior OF tb_serdes IS constant CLK_PERIOD : time := 10 ns; - constant MII_CLK_PERIOD : time := 8 ns; signal CLK : std_logic := '1'; signal RST : std_logic := '1'; - -- Slave - signal CYC_I : std_logic := '0'; - signal STB_I : std_logic := '0'; - signal WE_I : std_logic := '0'; - signal SEL_I : unsigned(3 downto 0); - signal ACK_O : std_logic; - signal INT_O : std_logic; - signal MRDY_I : std_logic; - signal SRDY_O : std_logic; - signal ADDR_I : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0) := (others => '-'); - signal DAT_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_O_reg : unsigned(31 downto 0) := (others => '-'); - - -- MII signals - signal mii_rx_clk_board : std_logic := '1'; - signal mii_tx_clk_board : std_logic := '1'; - signal mii_rx_clk : std_logic := '1'; - signal mii_tx_clk : std_logic := '1'; - signal mii_rx : unsigned(7 downto 0) := (others => '-'); - signal mii_tx : unsigned(7 downto 0); - signal mii_rx_dv : std_logic := '0'; - signal mii_rx_er : std_logic := '0'; - signal mii_tx_en : std_logic; - signal mii_tx_er : std_logic; - signal mii_crs : std_logic := '0'; - signal mii_col : std_logic := '0'; - signal mii_gtx_clk : std_logic; - - signal shift_sa : integer := 0; - signal shift_din_vld : std_logic := '0'; - signal shift_din : unsigned(31 downto 0) := (others => '-'); - signal shift_dout_vld : std_logic; - signal shift_dout : unsigned(31 downto 0); - signal piso_din_vld : std_logic := '0'; signal piso_din_rdy : std_logic; signal piso_din_be : unsigned(3 downto 0) := (others => '0'); @@ -106,65 +70,9 @@ ARCHITECTURE behavior OF tb_emac_jb IS signal sipo2_dout_be : unsigned(1 downto 0); signal sipo2_dout : unsigned(7 downto 0); - type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_read); - signal emac_action : emac_action_t; BEGIN -inst_emac_jb : entity work.emac_jb - GENERIC MAP - ( - f_sysclk => 100.0, - TX_RAM_SIZE => 2048 - ) - PORT MAP - ( - CLK_I => CLK, - RST_I => RST, - INT_O => INT_O, - CYC_I => CYC_I, - STB_I => STB_I, - SEL_I => SEL_I, - WE_I => WE_I, - ACK_O => ACK_O, - SRDY_O => SRDY_O, - MRDY_I => MRDY_I, - ADDR_I => ADDR_I, - DAT_I => DAT_I, - DAT_O => DAT_O, - mii_rx_clk => mii_rx_clk_board, - mii_rx_dv => mii_rx_dv, - mii_rx_er => mii_rx_er, - mii_rx => mii_rx, - mii_tx_clk => mii_tx_clk_board, - mii_tx_en => mii_tx_en, - mii_tx_er => mii_tx_er, - mii_tx => mii_tx, - mii_gtx_clk => mii_gtx_clk, - mii_crs => mii_crs, - mii_col => mii_col - - ); - -inst_shifter : entity work.shifter - GENERIC MAP - ( - data_width => 32, - aggregate_size => 4, - do_pipelined => true - ) - PORT MAP - ( - rst => RST, - clk => CLK, - sa => shift_sa, - din_vld => shift_din_vld, - din => shift_din, - dout_vld => shift_dout_vld, - dout => shift_dout - - ); - inst_piso : entity work.piso GENERIC MAP ( @@ -186,7 +94,7 @@ inst_piso : entity work.piso ); - piso_dout_en <= '0'; --piso2_din_rdy; + piso_dout_en <= piso2_din_rdy; inst_piso2 : entity work.piso GENERIC MAP @@ -269,206 +177,17 @@ CLK_GEN: process CLK <= not CLK; end process; -MII_CLK_GEN: process - begin - wait for MII_CLK_PERIOD/2; - mii_rx_clk <= not mii_rx_clk; - mii_tx_clk <= not mii_tx_clk; - end process; - - mii_rx_clk_board <= mii_rx_clk; - mii_tx_clk_board <= mii_tx_clk; - -DAT_O_register: - process(CLK) - begin - if rising_edge(CLK) then - if ACK_O = '1' then - DAT_O_reg <= DAT_O; - end if; - end if; - end process; - -- Master STIMULUS: process - procedure emac_alloc (size : natural) is - begin - - -- TX-ALLOCATION - -- set TX-size - emac_action <= emac_alloc; - CYC_I <= '1'; - wait until rising_edge(CLK) and SRDY_O = '1'; - DAT_I <= to_unsigned(size, 16) & X"55AA"; - STB_I <= '1'; - WE_I <= '1'; - ADDR_I <= X"0000_0004"; - wait until rising_edge(CLK) and SRDY_O = '1'; - STB_I <= '0'; - - -- set alloc request - CYC_I <= '1'; - wait until rising_edge(CLK) and SRDY_O = '1'; - DAT_I <= X"0001_0000"; - STB_I <= '1'; - WE_I <= '1'; - ADDR_I <= X"0000_0000"; - wait until rising_edge(CLK) and SRDY_O = '1'; - STB_I <= '0'; - - WE_I <= '0'; - - -- check alloc busy - check_bsy: - while (true) loop - CYC_I <= '1'; - wait until rising_edge(CLK) and SRDY_O = '1'; - STB_I <= '1'; - ADDR_I <= X"0000_0000"; - wait until rising_edge(CLK) and SRDY_O = '1'; - STB_I <= '0'; - wait until rising_edge(CLK) and ACK_O = '1'; - wait until rising_edge(CLK); - if DAT_O_reg(16) = '0' then - exit check_bsy; - end if; - end loop; - emac_action <= emac_idle; - - end procedure emac_alloc; - - procedure emac_write (size : natural) is - variable data : unsigned (7 downto 0); - variable num_words : natural; - begin - - -- FILL TX data - emac_action <= emac_write; - if (size mod 4) = 0 then - num_words := size/4; - else - num_words := size/4 + 1; - end if; - - CYC_I <= '1'; - wait until rising_edge(CLK) and SRDY_O = '1'; - data := X"00"; - ADDR_I <= X"0000_0008"; - WE_I <= '1'; - for i in 1 to num_words loop - STB_I <= '1'; - DAT_I(7 downto 0) <= data; - data := data + 1; - DAT_I(15 downto 8) <= data; - data := data + 1; - DAT_I(23 downto 16) <= data; - data := data + 1; - DAT_I(31 downto 24) <= data; - data := data + 1; - wait until rising_edge(CLK) and SRDY_O = '1'; - end loop; - - STB_I <= '0'; - wait until rising_edge(CLK) and SRDY_O = '1'; - emac_action <= emac_idle; - - end procedure emac_write; begin - wait for 6*MII_CLK_PERIOD; + wait for 600*CLK_PERIOD; RST <= '0'; wait for 60*CLK_PERIOD; --- emac_alloc (1536); --- emac_write (1536); --- --- emac_alloc (1536); --- emac_write (1536); --- --- emac_alloc (1536); --- emac_write (1536); --- --- emac_alloc (1536); --- emac_write (1536); --- --- emac_alloc (1536); --- emac_write (1536); --- --- emac_alloc (1536); --- emac_write (1536); --- --- emac_alloc (1536); --- emac_write (1536); --- --- emac_alloc (64); --- emac_write (64); --- --- emac_alloc (512); --- emac_write (512); --- --- emac_alloc (1536); --- emac_write (1536); --- --- emac_alloc (65); --- emac_write (65); --- --- emac_alloc (66); --- emac_write (66); --- --- emac_alloc (67); --- emac_write (67); --- --- emac_alloc (512); --- emac_write (64); --- --- emac_alloc (128); --- emac_write (128); - --- wait for 4000*CLK_PERIOD; --- --- wait until rising_edge(CLK); --- shift_din <= X"12345678"; --- shift_sa <= 0; --- shift_din_vld <= '1'; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa + 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa + 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa + 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa + 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa + 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa + 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa + 1; --- wait until rising_edge(CLK); --- --- shift_sa <= 0; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa - 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa - 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa - 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa - 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa - 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa - 1; --- wait until rising_edge(CLK); --- shift_sa <= shift_sa - 1; --- --- wait until rising_edge(CLK); --- shift_din_vld <= '0'; - - for i in 1 to 10 loop wait until rising_edge(CLK);