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VGA: refactored clocks and resets

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1593 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-30 06:50:08 +00:00
parent 5ffd02c06e
commit 756dc0ec5a
5 changed files with 39 additions and 46 deletions
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lib/VGA_ctrl/src/vga_frontend_jb64.vhd
+8 -10
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@@ -66,8 +66,8 @@ entity vga_frontend_jb64 is
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_clk : in std_logic;
vga_rst : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
@@ -97,7 +97,6 @@ architecture Behavioral of vga_frontend_jb64 is
signal color_op : color_op_t;
signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
signal stat_vga_rdy : std_logic;
signal stat_hready : std_logic;
signal stat_vready : std_logic;
signal stat_scan : std_logic;
@@ -413,7 +412,6 @@ inst_vga_backend : entity work.vga_backend
ctrl_scan_en => ctrl_scan_en,
-- Status signals
stat_vga_rdy => stat_vga_rdy,
stat_scan => stat_scan,
stat_hsync => stat_hsync,
stat_vsync => stat_vsync,
@@ -425,8 +423,8 @@ inst_vga_backend : entity work.vga_backend
stat_vpos => stat_vpos,
-- VGA domain signals
vga_clk_in => vga_clk_in,
vga_clk_ce => vga_clk_ce,
vga_clk => vga_clk,
vga_rst => vga_rst,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
@@ -466,7 +464,7 @@ inst_linefifo: entity work.fifo_async
(
rst => RST_I,
clk_w => CLK_I,
clk_r => vga_clk_in,
clk_r => vga_clk,
we => fifo_color_we,
re => fifo_color_re,
data_w => fifo_color_in,
@@ -600,7 +598,7 @@ vga_master_next:
end process;
vga_master:
process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_empty, blit_request, blit_dst_suspend, blit_chunk_full, blitfifo_dout_vld, blit_src_finish, blitfifo_empty_read, blit_dst_finish, blit_const_color_en)
process(s, vga_rst, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_empty, blit_request, blit_dst_suspend, blit_chunk_full, blitfifo_dout_vld, blit_src_finish, blitfifo_empty_read, blit_dst_finish, blit_const_color_en)
begin
CYC_O_scan <= '0';
@@ -616,7 +614,7 @@ vga_master:
sn <= s;
case s is
when init =>
if stat_vga_rdy = '1' then
if vga_rst = '0' then
sn <= rdy;
end if;
@@ -1057,7 +1055,7 @@ inst_char_gen : entity work.char_gen
(
rst => RST_I,
sys_clk => CLK_I,
vga_clk => vga_clk_in,
vga_clk => vga_clk,
ce => cg_en,
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,