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- rename 'page' to 'bank'

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git-svn-id: http://moon:8086/svn/vhdl/trunk@261 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-18 22:14:40 +00:00
parent cfb87bf755
commit 739921d7a9
3 changed files with 9 additions and 12 deletions
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lib/CPUs/JCpu/src/core/chipreg.vhd
+5 -5
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@@ -42,7 +42,7 @@ end chipreg;
architecture Behavioral of chipreg is
signal reg_page_sel : page_sel_t;
signal reg_bank_sel : bank_sel_t;
signal reg_int_ctrl : int_ctrl_in_t;
signal reg_stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
signal reg_cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
@@ -53,7 +53,7 @@ proc_assign_ctrl_lines:
process (clk)
begin
if rising_edge(clk) then
ctrl_out.page_sel <= reg_page_sel;
ctrl_out.bank_sel <= reg_bank_sel;
ctrl_out.int_ctrl <= reg_int_ctrl;
ctrl_out.stk_high <= reg_stk_high;
ctrl_out.cmem_high <= reg_cmem_high;
@@ -66,7 +66,7 @@ proc_reg_write:
if rst = '1' then
reg_stk_high <= (others => '0');
reg_cmem_high <= (others => '0');
reg_page_sel <= (others => '0');
reg_bank_sel <= (others => '0');
reg_int_ctrl.enable <= '0';
reg_int_ctrl.polarity <= '1';
reg_int_ctrl.edge_sens <= '1';
@@ -75,7 +75,7 @@ proc_reg_write:
if we = '1' then
case addr is
when X"01" =>
reg_page_sel(page_sel_t'range) <= din(page_sel_t'range);
reg_bank_sel(bank_sel_t'range) <= din(bank_sel_t'range);
when X"03" =>
reg_int_ctrl.enable <= din(0);
reg_int_ctrl.polarity <= din(1);
@@ -99,7 +99,7 @@ proc_reg_read:
when X"00" => -- Revison
dout <= to_unsigned(REVISION, dmem_data_t'length);
when X"01" => -- Control 0
dout <= (7 downto page_sel_t'length => '0') & reg_page_sel;
dout <= (7 downto bank_sel_t'length => '0') & reg_bank_sel;
when X"02" => -- CPU status
dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
when X"03" => -- Interrupt control