diff --git a/lib/CPUs/JCpu/src/core/chipreg.vhd b/lib/CPUs/JCpu/src/core/chipreg.vhd
index 483c627..97c109a 100644
--- a/lib/CPUs/JCpu/src/core/chipreg.vhd
+++ b/lib/CPUs/JCpu/src/core/chipreg.vhd
@@ -42,7 +42,7 @@ end chipreg;
 
 architecture Behavioral of chipreg is
 
-	signal reg_page_sel		: page_sel_t;
+	signal reg_bank_sel		: bank_sel_t;
 	signal reg_int_ctrl		: int_ctrl_in_t;
 	signal reg_stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
 	signal reg_cmem_high	: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
@@ -53,7 +53,7 @@ proc_assign_ctrl_lines:
 	process (clk)
 	begin
 		if rising_edge(clk) then
-			ctrl_out.page_sel	<= reg_page_sel;
+			ctrl_out.bank_sel	<= reg_bank_sel;
 			ctrl_out.int_ctrl	<= reg_int_ctrl;
 			ctrl_out.stk_high	<= reg_stk_high;
 			ctrl_out.cmem_high	<= reg_cmem_high;
@@ -66,7 +66,7 @@ proc_reg_write:
 		if rst = '1' then
 			reg_stk_high <= (others => '0');
 			reg_cmem_high <= (others => '0');
-			reg_page_sel <= (others => '0');
+			reg_bank_sel <= (others => '0');
 			reg_int_ctrl.enable		<= '0';
 			reg_int_ctrl.polarity	<= '1';
 			reg_int_ctrl.edge_sens	<= '1';
@@ -75,7 +75,7 @@ proc_reg_write:
 			if we = '1' then
 				case addr is
 				when X"01" =>
-					reg_page_sel(page_sel_t'range)	<= din(page_sel_t'range);
+					reg_bank_sel(bank_sel_t'range)	<= din(bank_sel_t'range);
 				when X"03" =>
 					reg_int_ctrl.enable		<= din(0);
 					reg_int_ctrl.polarity	<= din(1);
@@ -99,7 +99,7 @@ proc_reg_read:
 			when X"00" =>	-- Revison
 				dout <= to_unsigned(REVISION, dmem_data_t'length);
 			when X"01" =>	-- Control 0
-				dout <= (7 downto page_sel_t'length => '0') & reg_page_sel;
+				dout <= (7 downto bank_sel_t'length => '0') & reg_bank_sel;
 			when X"02" =>	-- CPU status
 				dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
 			when X"03" =>	-- Interrupt control
diff --git a/lib/CPUs/JCpu/src/core/cpu.vhd b/lib/CPUs/JCpu/src/core/cpu.vhd
index 1184806..06aeb33 100644
--- a/lib/CPUs/JCpu/src/core/cpu.vhd
+++ b/lib/CPUs/JCpu/src/core/cpu.vhd
@@ -221,7 +221,7 @@ begin
 	xmem_dout <= mem_data;
 	xmem_addr <= mem_addr;
 	cmem_din <= creg_ctrl_out.cmem_high & mem_data;
-	cmem_addr <= '1' & creg_ctrl_out.page_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.page_sel'length-1, mem_addr'length)-1 downto 0);
+	cmem_addr <= '1' & creg_ctrl_out.bank_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.bank_sel'length-1, mem_addr'length)-1 downto 0);
 
 --------------------------------------------------------------------
 mem_ctrl_lines:
@@ -368,7 +368,7 @@ mem_data_mux:
 	end process;
 
 mem_addr_mux:
-	process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.page_sel)
+	process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.bank_sel)
 	begin
 		case ctrl.lines.daddr_src_sel is
 		when reg_a => 
diff --git a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
index 4c4d56c..19afd28 100644
--- a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
+++ b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
@@ -34,9 +34,6 @@ package cpu_pkg is
 	-- Chipram depth (valid values 9..floor(log2(BlockRamBytes)))
 	constant CHIPRAM_SIZE_BITS : integer := 10;
 	
-	-- Chipregister file depth
-	constant CHIPREG_SIZE_BITS : integer := 8;
-
 	-- Number of registers (16 registers fixed)
 	constant REG_SIZE_BITS : integer := 4;
 	
@@ -75,7 +72,7 @@ package cpu_pkg is
 	subtype reg_ptr_t is unsigned (3 downto 0);
 	type dmem_array_t is array (natural range <>) of dmem_data_t;
 	type instr_addr_array is array (integer range <>) of inst_addr_t;
-	subtype page_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0);
+	subtype bank_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0);
 	
 	type alu_op_t is
 	(
@@ -142,7 +139,7 @@ package cpu_pkg is
 	end record;
 	
 	type creg_ctrl_out_t is record
-		page_sel		: page_sel_t;
+		bank_sel		: bank_sel_t;
 		int_ctrl		: int_ctrl_in_t;
 		stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
 		cmem_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);