jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- removed ram_wb

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@329 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-02-08 18:20:42 +00:00
parent fed261182c
commit 6ff7294c1e
6 changed files with 10 additions and 223 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys.vhd
+4 -51
View File
@@ -32,7 +32,6 @@ use UNISIM.vcomponents.all;
library work;
use work.mips_types.all;
--use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
use work.vga_types.all;
@@ -160,24 +159,6 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
COMPONENT ram_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT lcd_port
PORT
(
@@ -393,11 +374,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal SDAT_I_sdram : unsigned(63 downto 0);
signal SEL_I_sdram : unsigned(7 downto 0);
signal CYC_I_ram : std_logic;
signal ACK_O_ram : std_logic;
signal SRDY_O_ram : std_logic;
signal SDAT_O_ram : unsigned(31 downto 0);
signal CYC_I_rom : std_logic;
signal ACK_O_rom : std_logic;
signal SRDY_O_rom : std_logic;
@@ -440,7 +416,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
BEGIN
@@ -532,8 +508,7 @@ mem_mux:
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
mem_area <= mem_ram;
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sdram;
end if;
@@ -548,7 +523,6 @@ signal_mux:
CYC_I_flash <= '0';
CYC_I_usb <= '0';
CYC_I_rom <= '0';
CYC_I_ram <= '0';
CYC_I_sdram <= '0';
CYC_I_vga <= '0';
CYC_I_ac97 <= '0';
@@ -570,9 +544,6 @@ signal_mux:
when mem_rom =>
CYC_I_rom <= CYC_O;
when mem_ram =>
CYC_I_ram <= CYC_O;
when mem_sdram =>
CYC_I_sdram <= CYC_O;
@@ -589,10 +560,9 @@ signal_mux:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_ram when CYC_I_ram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
SDAT_O_flash when CYC_I_flash = '1' else
SDAT_O_usb when CYC_I_usb = '1' else
@@ -621,23 +591,6 @@ inst_mips_top: mips_top
INT => INT
);
inst_ram_wb : ram_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_ram,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_ram,
SRDY_O => SRDY_O_ram,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_ram
);
inst_rom_wb : rom_wb
PORT MAP
(
projects/mips_sys/src/mips_sys_sim.vhd
+5 -51
View File
@@ -170,24 +170,6 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
COMPONENT ram_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT lcd_port
PORT
(
@@ -450,11 +432,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal SDAT_I_sdram : unsigned(63 downto 0);
signal SEL_I_sdram : unsigned(7 downto 0);
signal CYC_I_ram : std_logic;
signal ACK_O_ram : std_logic;
signal SRDY_O_ram : std_logic;
signal SDAT_O_ram : unsigned(31 downto 0);
signal CYC_I_rom : std_logic;
signal ACK_O_rom : std_logic;
signal SRDY_O_rom : std_logic;
@@ -503,7 +480,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
BEGIN
@@ -623,9 +600,8 @@ mem_mux:
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
mem_area <= mem_ram;
-- mem_area <= mem_ssram;
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
-- kernel sram
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sdram;
end if;
@@ -640,7 +616,6 @@ signal_mux:
CYC_I_flash <= '0';
CYC_I_usb <= '0';
CYC_I_rom <= '0';
CYC_I_ram <= '0';
CYC_I_sdram <= '0';
CYC_I_vga <= '0';
CYC_I_ssram <= '0';
@@ -663,9 +638,6 @@ signal_mux:
when mem_rom =>
CYC_I_rom <= CYC_O;
when mem_ram =>
CYC_I_ram <= CYC_O;
when mem_sdram =>
CYC_I_sdram <= CYC_O;
@@ -685,11 +657,10 @@ signal_mux:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else
SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_ram when CYC_I_ram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
SDAT_O_flash when CYC_I_flash = '1' else
SDAT_O_usb when CYC_I_usb = '1' else
@@ -718,23 +689,6 @@ inst_mips_top: mips_top
INT => INT
);
inst_ram_wb : ram_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_ram,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_ram,
SRDY_O => SRDY_O_ram,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_ram
);
inst_rom_wb : rom_wb
PORT MAP
(