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- removed weird feature, which prevents cop registers to be written in front of exception.

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cop register behavior is now hopefully the same as general registers.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@421 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-03-30 23:29:33 +00:00
parent 2e1850c19b
commit 6983e7ebec
1 changed files with 10 additions and 7 deletions
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lib/CPUs/MIPS/src/core/mips_cop.vhd
+10 -7
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@@ -72,7 +72,6 @@ architecture Behavioral of cop is
signal exception_end : STD_LOGIC; signal exception_end : STD_LOGIC;
signal eflags : exc_flags_t; signal eflags : exc_flags_t;
signal exc_enable : STD_LOGIC; signal exc_enable : STD_LOGIC;
signal cop_EX_en : STD_LOGIC;
signal icache_info : unsigned(7 downto 0); signal icache_info : unsigned(7 downto 0);
signal dcache_info : unsigned(7 downto 0); signal dcache_info : unsigned(7 downto 0);
@@ -118,9 +117,8 @@ begin
cop_pipe_ID.rt <= extract_rt(ir); cop_pipe_ID.rt <= extract_rt(ir);
cop_pipe_ID.func <= extract_func(ir); cop_pipe_ID.func <= extract_func(ir);
cop_pipe_ID.CO <= ir(25); cop_pipe_ID.CO <= ir(25);
cop_pipe_ID.re <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "111000" or cop_pipe_ID.rs = "00000") else '0'; cop_pipe_ID.re <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "111000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00000")) else '0';
cop_pipe_ID.we <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "110000" or cop_pipe_ID.rs = "00100") else '0'; cop_pipe_ID.we <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "110000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00100")) else '0';
cop_EX_en <= exc_enable and not status_save;
ctrl_out.RE <= status(25); ctrl_out.RE <= status(25);
ctrl_out.user_mode <= status(1); ctrl_out.user_mode <= status(1);
@@ -319,8 +317,10 @@ cop_ip_reg_write:
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
ip(1 downto 0) <= (others => '0'); ip(1 downto 0) <= (others => '0');
elsif ip_reg_we = '1' then elsif ctrl_in.sdu.WB_nop = '0' then
ip(1 downto 0) <= din(9 downto 8) and im(1 downto 0); if ip_reg_we = '1' then
ip(1 downto 0) <= din(9 downto 8) and im(1 downto 0);
end if;
end if; end if;
ip(7 downto 2) <= ctrl_in.events.Int and im(7 downto 2); ip(7 downto 2) <= ctrl_in.events.Int and im(7 downto 2);
end if; end if;
@@ -386,6 +386,9 @@ cop_register_read:
end process; end process;
-- 18296365000 ps
-- 20158175000 ps
cop_we_gen: cop_we_gen:
process(clk) process(clk)
begin begin
@@ -398,7 +401,7 @@ cop_we_gen:
test_reg_we <= '0'; test_reg_we <= '0';
stat_reg_we <= '0'; stat_reg_we <= '0';
ip_reg_we <= '0'; ip_reg_we <= '0';
if (cop_EX_en and cop_pipe_EX.we) = '1' then if cop_pipe_EX.we = '1' then
case cop_pipe_EX.reg_ptr is case cop_pipe_EX.reg_ptr is