diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd index 357c5a7..ea917c6 100644 --- a/lib/CPUs/MIPS/src/core/mips_cop.vhd +++ b/lib/CPUs/MIPS/src/core/mips_cop.vhd @@ -72,7 +72,6 @@ architecture Behavioral of cop is signal exception_end : STD_LOGIC; signal eflags : exc_flags_t; signal exc_enable : STD_LOGIC; - signal cop_EX_en : STD_LOGIC; signal icache_info : unsigned(7 downto 0); signal dcache_info : unsigned(7 downto 0); @@ -118,9 +117,8 @@ begin cop_pipe_ID.rt <= extract_rt(ir); cop_pipe_ID.func <= extract_func(ir); cop_pipe_ID.CO <= ir(25); - cop_pipe_ID.re <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "111000" or cop_pipe_ID.rs = "00000") else '0'; - cop_pipe_ID.we <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "110000" or cop_pipe_ID.rs = "00100") else '0'; - cop_EX_en <= exc_enable and not status_save; + cop_pipe_ID.re <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "111000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00000")) else '0'; + cop_pipe_ID.we <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "110000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00100")) else '0'; ctrl_out.RE <= status(25); ctrl_out.user_mode <= status(1); @@ -319,8 +317,10 @@ cop_ip_reg_write: if rising_edge(clk) then if rst = '1' then ip(1 downto 0) <= (others => '0'); - elsif ip_reg_we = '1' then - ip(1 downto 0) <= din(9 downto 8) and im(1 downto 0); + elsif ctrl_in.sdu.WB_nop = '0' then + if ip_reg_we = '1' then + ip(1 downto 0) <= din(9 downto 8) and im(1 downto 0); + end if; end if; ip(7 downto 2) <= ctrl_in.events.Int and im(7 downto 2); end if; @@ -386,6 +386,9 @@ cop_register_read: end process; +-- 18296365000 ps +-- 20158175000 ps + cop_we_gen: process(clk) begin @@ -398,7 +401,7 @@ cop_we_gen: test_reg_we <= '0'; stat_reg_we <= '0'; ip_reg_we <= '0'; - if (cop_EX_en and cop_pipe_EX.we) = '1' then + if cop_pipe_EX.we = '1' then case cop_pipe_EX.reg_ptr is