- Intital revision

git-svn-id: http://moon:8086/svn/vhdl/trunk@86 cc03376c-175c-47c8-b038-4cd826a8556b

lib/misc/bbfifo.vhd

@@ -0,0 +1,123 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity bbfifo is
+	Generic 
+	(
+		depth	   : integer := 2;
+		data_width : integer := 8
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		ready		: out STD_LOGIC;
+		avail		: out STD_LOGIC;
+		din			: in  unsigned(data_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+end bbfifo;
+
+architecture Behavioral of bbfifo is
+
+	type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
+	signal req : unsigned(0 to depth);
+	signal rdy : unsigned(1 to depth+1);
+	signal bucket_array : bucket_array_t; 
+	signal ce_in : unsigned(1 to depth);
+	signal ce_out : unsigned(1 to depth);
+	
+begin
+	
+	req(0)			<= we;
+	rdy(depth+1)	<= re;
+	ready			<= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
+	avail			<= req(depth);
+	bucket_array(0)	<= din;
+	dout			<= bucket_array(depth);
+	
+gen_ce:
+	for i in 1 to depth generate
+	begin
+		process (rdy, req)
+		begin
+			ce_in(i) <= not req(i) and req(i-1);
+		end process;
+	end generate;
+
+gen_rdy:
+	for i in 1 to depth generate
+	begin
+		process (clk)
+		begin
+			if rising_edge(clk) then
+				if rst = '1' then
+					rdy(i) <= '1';
+				elsif req(i-1) = '1' then
+					rdy(i) <= rdy(i+1);
+				end if;
+			end if;
+		end process;
+	end generate;
+
+gen_req:
+	for i in 1 to depth generate
+	begin
+		process (clk)
+		begin
+			if rising_edge(clk) then
+				if rst = '1' then
+					req(i) <= '0';
+				elsif rdy(i+1) = '1' then
+					req(i) <= req(i-1);
+				end if;
+			end if;
+		end process;
+	end generate;
+
+gen_data:
+	for i in 1 to depth generate
+	begin
+		process (clk)
+		begin
+			if rising_edge(clk) then
+				if rst = '1' then
+					bucket_array(i) <= (others => '0');
+				elsif req(i-1) = '1' then
+					bucket_array(i) <= bucket_array(i-1);
+				end if;
+			end if;
+		end process;
+	end generate;
+
+end Behavioral;
+

lib/misc/gpio_wb.vhd

@@ -0,0 +1,211 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY gpio_wb IS
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+
+		sys_gpo0	: out unsigned(31 downto 0);
+		sys_gpo1	: out unsigned(31 downto 0);
+		sys_gpi0	: in  unsigned(31 downto 0);
+		sys_gpi1	: in  unsigned(31 downto 0)
+
+	);
+END gpio_wb;
+
+ARCHITECTURE behavior OF gpio_wb IS
+
+	signal gpo0_reg		: unsigned(31 downto 0);
+	signal gpo1_reg		: unsigned(31 downto 0);
+	signal gpi0_reg		: unsigned(31 downto 0);
+	signal gpi1_reg		: unsigned(31 downto 0);
+	-- Signals to form an timer generating an interrupt every microsecond
+	subtype tick_usec_t	is natural range 0 to 99;
+	signal tick_usec		: tick_usec_t;
+	signal cnt_usec			: unsigned(31 downto 0);
+	signal cnt_sec			: unsigned(31 downto 0);
+	signal cnt_usec_preset	: unsigned(31 downto 0);
+	signal cnt_sec_preset	: unsigned(31 downto 0);
+	signal cnt_usec_en		: std_logic;
+	signal cnt_usec_we		: std_logic;
+	signal cnt_sec_en		: std_logic;
+	signal cnt_sec_we		: std_logic;
+
+begin
+
+	SRDY_O	<= CYC_I;
+	
+------------------------------------------------------------------
+led_out:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			sys_gpo0	<= gpo0_reg;
+			sys_gpo1	<= gpo1_reg;
+		end if;
+	end process;	
+		
+------------------------------------------------------------------
+btn_ps2_in:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			gpi0_reg	<= sys_gpi0;
+			gpi1_reg	<= sys_gpi1;
+		end if;
+	end process;	
+		
+------------------------------------------------------------------
+registers_write: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			cnt_usec_we		<= '0';
+			cnt_sec_we		<= '0';
+			if RST_I = '1' then
+				gpo0_reg	<= (others => '0');
+				gpo1_reg	<= (others => '0');
+			elsif (STB_I and CYC_I and WE_I) = '1' then
+				case ADDR_I(5 downto 2) is
+				
+				when "0000" =>
+					if SEL_I(0) = '1' then
+						gpo0_reg(7 downto 0) <= DAT_I(7 downto 0);
+					end if;	
+					if SEL_I(1) = '1' then
+						gpo0_reg(15 downto 8) <= DAT_I(15 downto 8);
+					end if;	
+					if SEL_I(2) = '1' then
+						gpo0_reg(23 downto 16) <= DAT_I(23 downto 16);
+					end if;	
+					if SEL_I(3) = '1' then
+						gpo0_reg(31 downto 24) <= DAT_I(31 downto 24);
+					end if;	
+					
+				when "0001" =>
+					if SEL_I(0) = '1' then
+						gpo1_reg(7 downto 0) <= DAT_I(7 downto 0);
+					end if;	
+					if SEL_I(1) = '1' then
+						gpo1_reg(15 downto 8) <= DAT_I(15 downto 8);
+					end if;	
+					if SEL_I(2) = '1' then
+						gpo1_reg(23 downto 16) <= DAT_I(23 downto 16);
+					end if;	
+					if SEL_I(3) = '1' then
+						gpo1_reg(31 downto 24) <= DAT_I(31 downto 24);
+					end if;	
+					
+				when "0010" =>
+					if SEL_I(3) = '1' then
+						cnt_usec_we		<= '1';
+						cnt_usec_preset	<= DAT_I;
+					end if;	
+
+				when "0011" =>
+					if SEL_I(3) = '1' then
+						cnt_sec_we		<= '1';
+						cnt_sec_preset	<= DAT_I;
+					end if;	
+					
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+
+registers_read: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			ACK_O			<= '0';
+			if (STB_I and CYC_I) = '1' then
+				ACK_O		<= not WE_I;
+				DAT_O		<= (others => '0');
+				case ADDR_I(5 downto 2) is
+
+				when "0000" =>
+					DAT_O	<= gpi0_reg;
+
+				when "0001" =>
+					DAT_O	<= gpi1_reg;
+
+				when "0010" =>
+					DAT_O	<= cnt_usec;
+
+				when "0011" =>
+					DAT_O	<= cnt_sec;
+
+				when others => null;
+				end case;
+			end if;
+		end if;	
+	end process;
+
+tick_usec_timer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			cnt_usec_en		<= '0';
+			if RST_I = '1' then
+				tick_usec	<= 0;
+				cnt_usec_en	<= '0';
+			elsif tick_usec = tick_usec_t'high then
+				tick_usec		<= 0;
+				cnt_usec_en		<= '1';
+			else
+				tick_usec		<= tick_usec + 1;
+			end if;
+		end if;
+	end process;
+
+cnt_usec_timer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			cnt_sec_en		<= '0';
+			if RST_I = '1' then
+				cnt_usec	<= (others => '0');
+				cnt_sec_en	<= '0';
+			elsif cnt_usec_we = '1' then
+				cnt_usec		<= cnt_usec_preset;
+			elsif cnt_usec_en = '1' then
+				if cnt_usec = to_unsigned(1E6 - 1, 32) then
+					cnt_usec		<= (others => '0');
+					cnt_sec_en		<= '1';
+				else
+					cnt_usec		<= cnt_usec + 1;
+				end if;
+			end if;	
+		end if;
+	end process;
+
+cnt_sec_timer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				cnt_sec		<= (others => '0');
+			elsif cnt_sec_we = '1' then
+				cnt_sec		<= cnt_sec_preset;
+			elsif cnt_sec_en = '1' then
+				cnt_sec		<= cnt_sec + 1;
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------
+end behavior;

lib/misc/ram_sim.vhd

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY ram IS
+	Generic 
+	(
+		word_addr_width 	: integer := 6
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END ram;
+
+ARCHITECTURE behavior OF ram IS 
+
+	constant depth : natural := 2**word_addr_width;
+	
+	type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
+
+	function sram_clear return sram_t is
+
+	variable result : sram_t;
+	begin
+		for i in 0 to sram_t'length-1 loop
+			result(i) := (others => '0');
+		end loop;
+		return result;
+	end sram_clear;
+
+	signal sram : sram_t := sram_clear;
+	
+BEGIN
+
+
+SRAM_RW:
+	process(clk)
+	variable index : natural range 0 to depth-1;
+	begin
+		if rising_edge(clk) and ce = '1' then
+			index := to_integer(addr(word_addr_width+1 downto 2));
+			if we(0) = '1' then
+				sram(index)(7 downto 0)		<= din(7 downto 0);
+			end if;	
+			if we(1) = '1' then
+				sram(index)(15 downto 8)	<= din(15 downto 8);
+			end if;	
+			if we(2) = '1' then
+				sram(index)(23 downto 16)	<= din(23 downto 16);
+			end if;	
+			if we(3) = '1' then
+				sram(index)(31 downto 24)	<= din(31 downto 24);
+			end if;	
+			dout <= sram(index);
+		end if;	
+	end process;
+	
+end behavior;

lib/misc/ram_wb.vhd

@@ -0,0 +1,80 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY ram_wb IS
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0)
+	);
+END ram_wb;
+
+ARCHITECTURE behavior OF ram_wb IS
+
+	COMPONENT ram
+	GENERIC 
+	(
+		word_addr_width 	: integer
+	);
+	PORT 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	signal data_en : std_logic;
+	signal we : unsigned(3 downto 0);
+
+begin
+
+	we <= SEL_I and (3 downto 0 => WE_I);
+	
+	data_en	<= CYC_I and STB_I and MRDY_I;
+	SRDY_O	<= CYC_I;
+	
+data_valid_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ACK_O	<= '0';
+			else
+				ACK_O	<= data_en and not WE_I;
+			end if;
+		end if;
+	end process;
+
+inst_ram : ram
+	GENERIC MAP 
+	(
+		word_addr_width	=> 6
+	)
+	PORT MAP 
+	(
+		clk		=> CLK_I,
+		ce		=> data_en,
+		we		=> we,
+		addr	=> ADDR_I,
+		din		=> DAT_I,
+		dout	=> DAT_O
+	);
+
+
+
+end behavior;

lib/misc/rom_wb.vhd

@@ -0,0 +1,61 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY rom_wb IS
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0)
+	);
+END rom_wb;
+
+ARCHITECTURE behavior OF rom_wb IS
+
+	COMPONENT rom
+	PORT
+	(
+		clk		: in  STD_LOGIC;
+		ce		: in  STD_LOGIC;
+		addr	: in  unsigned(31 downto 0);
+		dout	: out unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	signal data_en : std_logic;
+
+begin
+
+	data_en	<= CYC_I and STB_I and MRDY_I;
+	SRDY_O	<= CYC_I;
+	
+data_valid_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ACK_O	<= '0';
+			else
+				ACK_O	<= data_en; -- and not WE_I;
+			end if;
+		end if;
+	end process;
+
+inst_rom : rom
+	PORT MAP
+	(
+		clk		=> CLK_I,
+		ce		=> data_en,
+		addr	=> ADDR_I,
+		dout	=> DAT_O
+	);
+
+
+end behavior;

lib/misc/sim/tb_bbfifo.fdo

@@ -0,0 +1,14 @@
+## NOTE:  Do not edit this file.
+##
+
+vlib work
+vcom -explicit  -93 "../bbfifo.vhd"
+vcom -explicit  -93 "../tb_bbfifo.vhd"
+
+#restart -force
+vsim -t 1ps   -lib work tb_bbfifo
+do {tb_bbfifo.wdo}
+view wave
+view structure
+view signals
+run 1us

lib/misc/sim/tb_bbfifo.wdo

@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_bbfifo/rst
+add wave -noupdate -format Logic /tb_bbfifo/clk
+add wave -noupdate -format Logic /tb_bbfifo/re
+add wave -noupdate -format Logic /tb_bbfifo/we
+add wave -noupdate -format Logic /tb_bbfifo/ready
+add wave -noupdate -format Logic /tb_bbfifo/avail
+add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout
+add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/req
+add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/rdy
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_bbfifo/inst_bbfifo/bucket_array
+add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_in
+add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_out
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {170000 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {76738 ps} {299465 ps}

lib/misc/sim/tb_ram_wb.fdo

@@ -0,0 +1,16 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+# Top and TB
+vcom -explicit  -93 "../ram_sim.vhd"
+vcom -explicit  -93 "../ram_wb.vhd"
+vcom -explicit  -93 "../tb_ram_wb.vhd"
+
+vsim -t 1ps   -lib work tb_ram_wb
+do {tb_ram_wb.wdo}
+view wave
+view structure
+view signals
+run 1.5us
+			 

lib/misc/sim/tb_ram_wb.wdo

@@ -0,0 +1,32 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_ram_wb/clk_o
+add wave -noupdate -format Logic /tb_ram_wb/rst_o
+add wave -noupdate -format Logic /tb_ram_wb/cyc_o
+add wave -noupdate -format Logic /tb_ram_wb/stb_o
+add wave -noupdate -format Logic /tb_ram_wb/we_o
+add wave -noupdate -format Literal /tb_ram_wb/sel_o
+add wave -noupdate -format Logic /tb_ram_wb/ack_i
+add wave -noupdate -format Logic /tb_ram_wb/mrdy_o
+add wave -noupdate -format Logic /tb_ram_wb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg
+add wave -noupdate -format Literal /tb_ram_wb/dout_cnt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {950000 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {1575 ns}

lib/misc/sim/tb_rom_wb.fdo

@@ -0,0 +1,16 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+# Top and TB
+vcom -explicit  -93 "../rom_sim.vhd"
+vcom -explicit  -93 "../rom_wb.vhd"
+vcom -explicit  -93 "../tb_rom_wb.vhd"
+
+vsim -t 1ps   -lib work tb_rom_wb
+do {tb_rom_wb.wdo}
+view wave
+view structure
+view signals
+run 1us
+			 

lib/misc/sim/tb_rom_wb.wdo

@@ -0,0 +1,29 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_rom_wb/clk_o
+add wave -noupdate -format Logic /tb_rom_wb/rst_o
+add wave -noupdate -format Logic /tb_rom_wb/cyc_o
+add wave -noupdate -format Logic /tb_rom_wb/stb_o
+add wave -noupdate -format Logic /tb_rom_wb/ack_i
+add wave -noupdate -format Logic /tb_rom_wb/mrdy_o
+add wave -noupdate -format Logic /tb_rom_wb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dout_reg
+add wave -noupdate -format Literal /tb_rom_wb/dout_cnt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {796036 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {1050 ns}

lib/misc/tb_bbfifo.vhd

@@ -0,0 +1,136 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity tb_bbfifo is
+end;
+
+architecture behave of tb_bbfifo is
+
+	-- Number of user data words for simulation
+	constant CLK_PERIOD		: time := 10 ns;
+
+	signal rst				: std_logic := '1';  
+	signal clk				: std_logic := '1';  
+	signal re				: std_logic := '0';  
+	signal we				: std_logic := '0';  
+	signal ready			: std_logic;  
+	signal avail			: std_logic;  
+	signal din				: unsigned(7 downto 0) := (others => '0');
+	signal dout				: unsigned(7 downto 0);
+	signal dout_reg			: unsigned(7 downto 0);
+
+
+begin 
+   
+inst_bbfifo : entity work.bbfifo
+	GENERIC MAP 
+	(
+		depth		=> 4,
+		data_width	=> 8
+	)
+	PORT MAP
+	(
+		rst		=> rst,
+		clk		=> clk,
+		re		=> re,
+		we		=> we,
+		ready	=> ready,
+		avail	=> avail,
+		din		=> din,
+		dout	=> dout
+	);
+
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+RE_GEN: process
+	begin
+		wait for 2*CLK_PERIOD;
+		wait until rising_edge(clk) and avail = '1';
+		re <= '0';
+		dout_reg <= dout;
+		wait until rising_edge(clk);
+		re <= '0';
+	end process;
+
+------------------------------------------------------------------------------------------
+
+STIMULUS: process
+
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		din <= X"10";
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		wait until rising_edge(clk) and ready = '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '0';
+		wait until rising_edge(clk) and ready = '1';
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '0';
+		wait until rising_edge(clk) and ready = '1';
+		wait until rising_edge(clk) and ready = '1';
+		wait until rising_edge(clk) and ready = '1';
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		
+
+		wait; 
+	
+	end process;
+	
+end architecture behave;

lib/misc/tb_ram_wb.vhd

@@ -0,0 +1,408 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+ENTITY tb_ram_wb IS
+END tb_ram_wb;
+
+ARCHITECTURE behavior OF tb_ram_wb IS 
+
+	constant CLK_PERIOD : time := 10 ns;
+	signal CLK_O	: std_logic := '1';
+	signal RST_O	: std_logic := '1';
+	signal CYC_O	: std_logic := '0';
+	signal STB_O	: std_logic := '0';
+	signal WE_O		: std_logic := '0';
+	signal SEL_O	: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I	: std_logic;
+	signal MRDY_O	: std_logic := '1';
+	signal SRDY_I	: std_logic;
+	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I	: unsigned(31 downto 0);
+	signal DAT_O	: unsigned(31 downto 0) := (others => '-');
+
+	signal dout_rst			: std_logic := '0';
+	signal dout_reg			: unsigned(31 downto 0);
+	signal dout_cnt			: natural range 0 to 255;
+
+BEGIN
+
+inst_ram_wb : entity work.ram_wb
+	PORT MAP
+	(
+		RST_I		=> RST_O,
+		CLK_I		=> CLK_O,
+		CYC_I		=> CYC_O,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_I,
+		SRDY_O		=> SRDY_I,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_I
+	);
+
+read_register:
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if dout_rst = '1' then
+				dout_cnt <= 0;
+			elsif ACK_I = '1' and WE_O = '0' then
+				dout_reg	<= DAT_I;
+				dout_cnt 	<= dout_cnt + 1;
+			end if;
+		end if;
+	end process;
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		RST_O <= '0';
+
+		-- 8 single cycles
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		DAT_O	<= X"1234_0000";
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		
+		-- 8-word burst cycle
+		wait for 3*CLK_PERIOD;
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and dout_cnt = 7;
+		CYC_O	<= '0';
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SEL_O	<= "0011";
+		ADDR_O	<= X"0000_0080";
+		DAT_O	<= X"DEADBEEF";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0080";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		-- 8-word burst cycle
+		wait for 3*CLK_PERIOD;
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		MRDY_O	<= '0';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		MRDY_O	<= '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and dout_cnt = 54;
+		CYC_O	<= '0';
+
+		wait; 
+	
+	end process;
+	
+END;

lib/misc/tb_rom_wb.vhd

@@ -0,0 +1,223 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+ENTITY tb_rom_wb IS
+END tb_rom_wb;
+
+ARCHITECTURE behavior OF tb_rom_wb IS 
+
+	constant CLK_PERIOD : time := 10 ns;
+	signal CLK_O	: std_logic := '1';
+	signal RST_O	: std_logic := '1';
+	signal CYC_O	: std_logic := '0';
+	signal STB_O	: std_logic := '0';
+	signal ACK_I	: std_logic;
+	signal MRDY_O	: std_logic := '1';
+	signal SRDY_I	: std_logic;
+	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I	: unsigned(31 downto 0);
+
+	signal dout_rst			: std_logic := '0';
+	signal dout_reg			: unsigned(31 downto 0);
+	signal dout_cnt			: natural range 0 to 255;
+
+BEGIN
+
+inst_rom_wb : entity work.rom_wb
+	PORT MAP
+	(
+		RST_I		=> RST_O,
+		CLK_I		=> CLK_O,
+		CYC_I		=> CYC_O,
+		STB_I		=> STB_O,
+		ACK_O		=> ACK_I,
+		SRDY_O		=> SRDY_I,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_O		=> DAT_I
+	);
+
+read_register:
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if dout_rst = '1' then
+				dout_cnt <= 0;
+			elsif ACK_I = '1' then
+				dout_reg	<= DAT_I;
+				dout_cnt 	<= dout_cnt + 1;
+			end if;
+		end if;
+	end process;
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		RST_O <= '0';
+
+		-- 8-word burst cycle
+		wait for 3*CLK_PERIOD;
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		ADDR_O	<= X"0000_0180";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		MRDY_O	<= '0';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		MRDY_O	<= '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and dout_cnt = 54;
+		CYC_O	<= '0';
+
+		wait; 
+	
+	end process;
+	
+END;