From 69697d72229a1a4d2eee3afc1d093653b36b6d1a Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Mon, 20 Oct 2008 19:26:01 +0000 Subject: [PATCH] - Intital revision git-svn-id: http://moon:8086/svn/vhdl/trunk@86 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/SSRAM/sim/ModelSim SE .lnk | Bin 0 -> 659 bytes lib/SSRAM/sim/tb_ssram_frontend_wb.fdo | 17 + lib/SSRAM/sim/tb_ssram_frontend_wb.wdo | 47 + lib/SSRAM/src/CY7C1354B.vhd | 388 +++++ lib/SSRAM/src/package_utility.vhd | 73 + lib/SSRAM/src/ssram_frontend_wb.vhd | 181 ++ lib/SSRAM/src/tb_ssram_frontend_wb.vhd | 457 ++++++ lib/VGA_ctrl/sim/ModelSim SE .lnk | Bin 0 -> 665 bytes lib/misc/bbfifo.vhd | 123 ++ lib/misc/gpio_wb.vhd | 211 +++ lib/misc/ram_sim.vhd | 88 + lib/misc/ram_wb.vhd | 80 + lib/misc/rom_sim.vhd | 2082 ++++++++++++++++++++++++ lib/misc/rom_wb.vhd | 61 + lib/misc/sim/ModelSim SE .lnk | Bin 0 -> 657 bytes lib/misc/sim/tb_bbfifo.fdo | 14 + lib/misc/sim/tb_bbfifo.wdo | 31 + lib/misc/sim/tb_ram_wb.fdo | 16 + lib/misc/sim/tb_ram_wb.wdo | 32 + lib/misc/sim/tb_rom_wb.fdo | 16 + lib/misc/sim/tb_rom_wb.wdo | 29 + lib/misc/tb_bbfifo.vhd | 136 ++ lib/misc/tb_ram_wb.vhd | 408 +++++ lib/misc/tb_rom_wb.vhd | 223 +++ 24 files changed, 4713 insertions(+) create mode 100644 lib/SSRAM/sim/ModelSim SE .lnk create mode 100644 lib/SSRAM/sim/tb_ssram_frontend_wb.fdo create mode 100644 lib/SSRAM/sim/tb_ssram_frontend_wb.wdo create mode 100644 lib/SSRAM/src/CY7C1354B.vhd create mode 100644 lib/SSRAM/src/package_utility.vhd create mode 100644 lib/SSRAM/src/ssram_frontend_wb.vhd create mode 100644 lib/SSRAM/src/tb_ssram_frontend_wb.vhd create mode 100644 lib/VGA_ctrl/sim/ModelSim SE .lnk create mode 100644 lib/misc/bbfifo.vhd create mode 100644 lib/misc/gpio_wb.vhd create mode 100644 lib/misc/ram_sim.vhd create mode 100644 lib/misc/ram_wb.vhd create mode 100644 lib/misc/rom_sim.vhd create mode 100644 lib/misc/rom_wb.vhd create mode 100644 lib/misc/sim/ModelSim SE .lnk create mode 100644 lib/misc/sim/tb_bbfifo.fdo create mode 100644 lib/misc/sim/tb_bbfifo.wdo create mode 100644 lib/misc/sim/tb_ram_wb.fdo create mode 100644 lib/misc/sim/tb_ram_wb.wdo create mode 100644 lib/misc/sim/tb_rom_wb.fdo create mode 100644 lib/misc/sim/tb_rom_wb.wdo create mode 100644 lib/misc/tb_bbfifo.vhd create mode 100644 lib/misc/tb_ram_wb.vhd create mode 100644 lib/misc/tb_rom_wb.vhd diff --git a/lib/SSRAM/sim/ModelSim SE .lnk b/lib/SSRAM/sim/ModelSim SE .lnk new file mode 100644 index 0000000000000000000000000000000000000000..0cc072f6d1ddcc6a36e0604ac736493698da598a GIT binary patch literal 659 zcmeZaU|?VrVFHp23k2A(p47hyYauFcdN5Go%B_M21`-Oa+QbF!(`D*l+PGQ-HzO z-^JA@q|Q*!$eFzU_ySEx0qV?QC;^hm3>ggZ3}y^^3`RgU1A`Qh z4ROzYi@!kA$}{tfjTn^R=DdfSQ_hgdkjG#Q)W^Ue!r%j9np2#a ztCv~7g3OZCA_xaarUiF= w$Wl@CT=a-Zj|%JG73{pkAi6%K<1-<7kUv-%7#64j>3pcE0BmZOYybcN literal 0 HcmV?d00001 diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo new file mode 100644 index 0000000..9aafbb0 --- /dev/null +++ b/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo @@ -0,0 +1,17 @@ +## NOTE: Do not edit this file. +## +vlib work + +# Top and TB +vcom -explicit -93 "../src/package_utility.vhd" +vcom -explicit -93 "../src/CY7C1354B.vhd" +vcom -explicit -93 "../src/ssram_frontend_wb.vhd" +vcom -explicit -93 "../src/tb_ssram_frontend_wb.vhd" + +vsim -t 1ps -lib work tb_ssram_frontend_wb +do {tb_ssram_frontend_wb.wdo} +view wave +view structure +view signals +run 6us + \ No newline at end of file diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo new file mode 100644 index 0000000..71718ed --- /dev/null +++ b/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo @@ -0,0 +1,47 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_ssram_frontend_wb/clk_o +add wave -noupdate -format Logic /tb_ssram_frontend_wb/rst_o +add wave -noupdate -format Logic /tb_ssram_frontend_wb/cyc_o +add wave -noupdate -format Logic /tb_ssram_frontend_wb/stb_o +add wave -noupdate -format Logic /tb_ssram_frontend_wb/we_o +add wave -noupdate -format Literal /tb_ssram_frontend_wb/sel_o +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ack_i +add wave -noupdate -format Logic /tb_ssram_frontend_wb/mrdy_o +add wave -noupdate -format Logic /tb_ssram_frontend_wb/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_o +add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_d +add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_dp +add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_a +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_cke_n +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_adv +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_mode +add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_bw_n +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_we_n +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_oe_n +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_ce_n +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_zz +add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dout_reg +add wave -noupdate -format Literal -radix unsigned /tb_ssram_frontend_wb/dout_cnt +add wave -noupdate -format Literal /tb_ssram_frontend_wb/inst_ssram_frontend_wb/vld_pipe +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk_fb +add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {1343191 ps} 0} {{Cursor 2} {178651436 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {6300 ns} diff --git a/lib/SSRAM/src/CY7C1354B.vhd b/lib/SSRAM/src/CY7C1354B.vhd new file mode 100644 index 0000000..d652656 --- /dev/null +++ b/lib/SSRAM/src/CY7C1354B.vhd @@ -0,0 +1,388 @@ +----------------------------------------------------------------------------------------- +-- +-- File Name: CY7C1354B.VHD +-- Version: 2.0 +-- Date: Nov 22nd, 2004 +-- Model: BUS Functional +-- +-- +-- Author: RKF +-- Company: Cypress Semiconductor +-- Model: CY7C1354B (256k x 36) +-- Mode: Pipelined +-- +-- Description: NoBL SRAM VHDL Model +-- +-- Limitation: None +-- +-- Note: - BSDL Model available separately +-- - Set simulator resolution to "ps" timescale +-- +-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +-- +-- Copyright (c) 2004 Cypress Semiconductor +-- All rights reserved +-- +-- Trademarks: NoBL and No Bus Latency are trademarks of Cypress Semiconductor +-- +-- Rev Author Date Changes +-- --- -------- ------- ---------- +-- 2.0 RKF 11/22/2004 - Second Release +-- - Fully Tested with New Test Bench and Test Vectors +----------------------------------------------------------------------------------------- + +LIBRARY ieee,work; + USE ieee.std_logic_1164.all; + USE ieee.std_logic_unsigned.all; + Use IEEE.Std_Logic_Arith.all; +-- Use work.all; + USE work.package_utility.all; + +ENTITY cy7c1354 IS + + GENERIC ( + + -- Constant parameters + addr_bits : INTEGER := 18; + data_bits : INTEGER := 32; + par_bits : INTEGER := 4; + + -- Timing parameters for -5 (225 Mhz) +-- tCYC : TIME := 4.4 ns; +-- tCH : TIME := 1.8 ns; +-- tCL : TIME := 1.8 ns; +-- tCO : TIME := 2.8 ns; +-- tAS : TIME := 1.4 ns; +-- tCENS : TIME := 1.4 ns; +-- tWES : TIME := 1.4 ns; +-- tDS : TIME := 1.4 ns; +-- tAH : TIME := 0.4 ns; +-- tCENH : TIME := 0.4 ns; +-- tWEH : TIME := 0.4 ns; +-- tDH : TIME := 0.4 ns + + + + -- Timing parameters for -6 (200 Mhz) + --tCYC : TIME := 5.0 ns; + --tCH : TIME := 2.0 ns; + --tCL : TIME := 2.0 ns; + --tCO : TIME := 3.2 ns; + --tAS : TIME := 1.5 ns; + --tCENS : TIME := 1.5 ns; + --tWES : TIME := 1.5 ns; + --tDS : TIME := 1.5 ns; + --tAH : TIME := 0.5 ns; + --tCENH : TIME := 0.5 ns; + --tWEH : TIME := 0.5 ns; + --tDH : TIME := 0.5 ns + + + -- Timing parameters for -7 (166 Mhz) + tCYC : TIME := 6.0 ns; + tCH : TIME := 2.4 ns; + tCL : TIME := 2.4 ns; + tCO : TIME := 3.5 ns; + tAS : TIME := 1.5 ns; + tCENS : TIME := 1.5 ns; + tWES : TIME := 1.5 ns; + tDS : TIME := 1.5 ns; + tAH : TIME := 0.5 ns; + tCENH : TIME := 0.5 ns; + tWEH : TIME := 0.5 ns; + tDH : TIME := 0.5 ns + + + + ); + + -- Port Declarations + PORT ( + Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O + Dpq : INOUT STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0); -- Data parity I/O + Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address + Mode : IN STD_LOGIC := '1'; -- Burst Mode + Clk : IN STD_LOGIC; -- Clk + CEN_n : IN STD_LOGIC; -- CEN# + AdvLd_n : IN STD_LOGIC; -- Adv/Ld# + Bwa_n : IN STD_LOGIC; -- Bwa# + Bwb_n : IN STD_LOGIC; -- BWb# + Bwc_n : IN STD_LOGIC; -- Bwc# + Bwd_n : IN STD_LOGIC; -- BWd# + Rw_n : IN STD_LOGIC; -- RW# + Oe_n : IN STD_LOGIC; -- OE# + Ce1_n : IN STD_LOGIC; -- CE1# + Ce2 : IN STD_LOGIC; -- CE2 + Ce3_n : IN STD_LOGIC; -- CE3# + Zz : IN STD_LOGIC -- Snooze Mode + ); +END cy7c1354; + +ARCHITECTURE behave OF cy7c1354 IS + SIGNAL ce : STD_LOGIC := '0'; + SIGNAL doe : STD_LOGIC := '0'; + SIGNAL dout : STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0) := (OTHERS => 'Z'); + SIGNAL dout_p : STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0) := (OTHERS => 'Z'); + SIGNAL Addr_read_sig : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => 'Z'); + +BEGIN + + + ce <= NOT(Ce1_n) AND NOT(Ce3_n) AND Ce2; + + doe <= NOT(Oe_n) AND NOT(Zz); + + -- Output Buffers + WITH doe SELECT + Dq <= TRANSPORT dout AFTER (tCO) WHEN '1', + (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS; + + WITH doe SELECT + Dpq <= TRANSPORT dout_p AFTER (tCO) WHEN '1', + (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS; + + + -- Check for Clock Timing Violation + clk_check : PROCESS + VARIABLE clk_high, clk_low : TIME := 0 ns; + BEGIN + WAIT ON Clk; + IF Clk = '1' AND NOW >= tCYC THEN + ASSERT (NOW - clk_low >= tCH) + REPORT "Clk width low - tCH violation" + SEVERITY ERROR; + ASSERT (NOW - clk_high >= tCYC) + REPORT "Clk period high - tCYC violation" + SEVERITY ERROR; + clk_high := NOW; + ELSIF Clk = '0' AND NOW /= 0 ns THEN + ASSERT (NOW - clk_high >= tCL) + REPORT "Clk width high - tCL violation" + SEVERITY ERROR; + ASSERT (NOW - clk_low >= tCYC) + REPORT "Clk period low - tCYC violation" + SEVERITY ERROR; + clk_low := NOW; + END IF; + END PROCESS; + + -- Check for Setup Timing Violation + setup_check : PROCESS + BEGIN + WAIT ON Clk; + IF Clk = '1' and (Ce1_n = '0' and Ce2 = '1' and Ce3_n = '0') THEN + ASSERT (Addr'LAST_EVENT >= tAS) + REPORT "Addr - tAS violation" + SEVERITY ERROR; + ASSERT (CEN_n'LAST_EVENT >= tCENS) + REPORT "CKE# - tCENS violation" + SEVERITY ERROR; + ASSERT (Ce1_n'LAST_EVENT >= tWES) + REPORT "CE1# - tWES violation" + SEVERITY ERROR; + ASSERT (Ce2'LAST_EVENT >= tWES) + REPORT "CE2 - tWES violation" + SEVERITY ERROR; + ASSERT (Ce3_n'LAST_EVENT >= tWES) + REPORT "CE3# - tWES violation" + SEVERITY ERROR; + ASSERT (AdvLd_n'LAST_EVENT >= tWES) + REPORT "ADV/LD# - tWES violation" + SEVERITY ERROR; + ASSERT (Rw_n'LAST_EVENT >= tWES) + REPORT "RW# - tWES violation" + SEVERITY ERROR; + ASSERT (Bwa_n'LAST_EVENT >= tWES) + REPORT "BWa# - tWES violation" + SEVERITY ERROR; + ASSERT (Bwb_n'LAST_EVENT >= tWES) + REPORT "BWb# - tWES violation" + SEVERITY ERROR; + ASSERT (Bwc_n'LAST_EVENT >= tWES) + REPORT "BWc# - tWES violation" + SEVERITY ERROR; + ASSERT (Bwd_n'LAST_EVENT >= tWES) + REPORT "BWd# - tWES violation" + SEVERITY ERROR; + ASSERT (Dq'LAST_EVENT >= tDS) + REPORT "Dq - tDS violation" + SEVERITY ERROR; + END IF; + END PROCESS; + + -- Check for Hold Timing Violation + hold_check : PROCESS + BEGIN + WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH); + IF Clk'DELAYED(tAH) = '1' THEN + ASSERT (Addr'LAST_EVENT > tAH) + REPORT "Addr - tAH violation" + SEVERITY ERROR; + END IF; + IF Clk'DELAYED(tCENH) = '1' THEN + ASSERT (CEN_n'LAST_EVENT > tCENH) + REPORT "CKE# - tCENH violation" + SEVERITY ERROR; + END IF; + IF Clk'DELAYED(tDH) = '1' THEN + ASSERT (Dq'LAST_EVENT > tDH) + REPORT "Dq - tDH violation" + SEVERITY ERROR; + END IF; + IF Clk'DELAYED(tWEH) = '1' THEN + ASSERT (Ce1_n'LAST_EVENT > tWEH) + REPORT "CE1# - tWEH violation" + SEVERITY ERROR; + ASSERT (Ce2'LAST_EVENT > tWEH) + REPORT "CE2 - tWEH violation" + SEVERITY ERROR; + ASSERT (Ce3_n'LAST_EVENT > tWEH) + REPORT "CE3 - tWEH violation" + SEVERITY ERROR; + ASSERT (AdvLd_n'LAST_EVENT > tWEH) + REPORT "ADV/LD# - tWEH violation" + SEVERITY ERROR; + ASSERT (Rw_n'LAST_EVENT > tWEH) + REPORT "RW# - tWEH violation" + SEVERITY ERROR; + ASSERT (Bwa_n'LAST_EVENT > tWEH) + REPORT "BWa# - tWEH violation" + SEVERITY ERROR; + ASSERT (Bwb_n'LAST_EVENT > tWEH) + REPORT "BWb# - tWEH violation" + SEVERITY ERROR; + ASSERT (Bwc_n'LAST_EVENT > tWEH) + REPORT "BWc# - tWEH violation" + SEVERITY ERROR; + ASSERT (Bwd_n'LAST_EVENT > tWEH) + REPORT "BWd# - tWEH violation" + SEVERITY ERROR; + END IF; + + END PROCESS; + + -- Main Program + main : PROCESS + + TYPE memory_array IS ARRAY ((2**addr_bits) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (((data_bits+par_bits) / 4) - 1 DOWNTO 0); + + VARIABLE Addr_in : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0'); + VARIABLE first_Addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Addr_read : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0'); + VARIABLE Addr_write : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0'); + VARIABLE bAddr0, bAddr1 : STD_LOGIC := '0'; + VARIABLE bank0 : memory_array; + VARIABLE bank1 : memory_array; + VARIABLE bank2 : memory_array; + VARIABLE bank3 : memory_array; + + VARIABLE ce_in : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE rw_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "111"; + VARIABLE bwa_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; + VARIABLE bwb_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; + VARIABLE bwc_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; + VARIABLE bwd_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; + VARIABLE bcnt : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + + BEGIN + WAIT ON Clk; + IF Clk'EVENT AND Clk = '1' THEN + IF CEN_n = '0' AND Zz = '0' THEN + -- Write Address Register + Addr_write := Addr_read; + + -- Read Address Register + Addr_read := Addr_in ((addr_bits - 1) DOWNTO 2) & bAddr1 & bAddr0; + + -- Address Register + IF AdvLd_n = '0' and ce = '1' THEN + Addr_in := Addr; + first_Addr := Addr(1 DOWNTO 0); + bcnt := Addr(1 DOWNTO 0); + END IF; + + + -- Burst Logic + IF Mode = '0' AND AdvLd_n = '1' THEN + bcnt := bcnt + 1; + ELSIF Mode = '1' AND AdvLd_n = '1' THEN + IF (CONV_INTEGER1 (first_Addr) REM 2 = 0) THEN + bcnt := bcnt + 1; + ELSIF (CONV_INTEGER1 (first_Addr) REM 2 = 1) THEN + bcnt := bcnt - 1; + END IF; + END IF; + + + bAddr1 := bcnt (1); + bAddr0 := bcnt (0); + + -- Read Logic + ce_in (0) := ce_in (1); + + IF AdvLd_n = '0' THEN + ce_in (1) := ce; + END IF; + + rw_in (0) := rw_in (1); + rw_in (1) := rw_in (2); + + IF AdvLd_n = '0' THEN + rw_in (2) := NOT(ce AND NOT(Rw_n)); + END IF; + + -- Write Registry and Data Coherency Control Logic + bwa_in (0) := bwa_in (1); + bwb_in (0) := bwb_in (1); + bwc_in (0) := bwc_in (1); + bwd_in (0) := bwd_in (1); + bwa_in (1) := bwa_in (2); + bwb_in (1) := bwb_in (2); + bwc_in (1) := bwc_in (2); + bwd_in (1) := bwd_in (2); + bwa_in (2) := Bwa_n; + bwb_in (2) := Bwb_n; + bwc_in (2) := Bwc_n; + bwd_in (2) := Bwd_n; + + -- Write Data to Memory + IF rw_in (0) = '0' AND bwa_in (0) = '0' THEN + bank0 (CONV_INTEGER1 (Addr_write)) := Dpq(0) & Dq ( (data_bits / 4) - 1 DOWNTO 0); + END IF; + IF rw_in (0) = '0' AND bwb_in (0) = '0' THEN + bank1 (CONV_INTEGER1 (Addr_write)) := Dpq(1) & Dq ((data_bits / 2 - 1) DOWNTO (data_bits / 4)); + END IF; + IF rw_in (0) = '0' AND bwc_in (0) = '0' THEN + bank2 (CONV_INTEGER1 (Addr_write)) := Dpq(2) & Dq ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2)); + END IF; + IF rw_in (0) = '0' AND bwd_in (0) = '0' THEN + bank3 (CONV_INTEGER1 (Addr_write)) := Dpq(3) & Dq (data_bits - 1 DOWNTO (3 * (data_bits / 4))); + END IF; + END IF; + + Addr_read_sig <= Addr_read; + + -- Read Data from Memory Array + IF ce_in (0) = '1' AND rw_in (1) = '1' THEN + dout ((data_bits / 4) - 1 DOWNTO 0) <= bank0 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); + dout ((data_bits / 2 - 1) DOWNTO (data_bits / 4)) <= bank1 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); + dout ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2)) <= bank2 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); + dout (data_bits - 1 DOWNTO (3 * (data_bits / 4))) <= bank3 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); + dout_p(0) <= bank0 (CONV_INTEGER1 (Addr_read))(data_bits / 4); + dout_p(1) <= bank1 (CONV_INTEGER1 (Addr_read))(data_bits / 4); + dout_p(2) <= bank2 (CONV_INTEGER1 (Addr_read))(data_bits / 4); + dout_p(3) <= bank3 (CONV_INTEGER1 (Addr_read))(data_bits / 4); + ELSE + dout <= (OTHERS => 'Z'); + dout_p <= (OTHERS => 'Z'); + END IF; + END IF; + END PROCESS; + +END behave; + + + diff --git a/lib/SSRAM/src/package_utility.vhd b/lib/SSRAM/src/package_utility.vhd new file mode 100644 index 0000000..9fb543f --- /dev/null +++ b/lib/SSRAM/src/package_utility.vhd @@ -0,0 +1,73 @@ +--**************************************************************** +--** MODEL : package_utility ** +--** COMPANY : Cypress Semiconductor ** +--** REVISION: 1.0 Created new package utility model ** +--** ** +--**************************************************************** +Library ieee,work; + Use ieee.std_logic_1164.all; + Use IEEE.Std_Logic_Arith.all; + Use IEEE.std_logic_TextIO.all; + --- Use work.package_timing.all; + +Library Std; + Use STD.TextIO.all; + +Package package_utility is + +FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR; +FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER; + +End; -- package package_utility + +Package body package_utility is + + +------------------------------------------------------------------------------------------------ +--Converts string into std_logic_vector +------------------------------------------------------------------------------------------------ + +FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS + VARIABLE result : STD_LOGIC_VECTOR(S'RANGE); + BEGIN + FOR i IN S'RANGE LOOP + IF S(i) = '0' THEN + result(i) := '0'; + ELSIF S(i) = '1' THEN + result(i) := '1'; + ELSIF S(i) = 'X' THEN + result(i) := 'X'; + ELSE + result(i) := 'Z'; + END IF; + END LOOP; + RETURN result; +END convert_string; + +------------------------------------------------------------------------------------------------ +--Converts std_logic_vector into integer +------------------------------------------------------------------------------------------------ + +FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + BEGIN + FOR i IN S'RANGE LOOP + IF S(i) = '1' THEN + result := result + (2**i); + ELSIF S(i) = '0' THEN + result := result; + ELSE + result := 0; + END IF; + END LOOP; + RETURN result; + END CONV_INTEGER1; + + + + +end package_utility; + + + + diff --git a/lib/SSRAM/src/ssram_frontend_wb.vhd b/lib/SSRAM/src/ssram_frontend_wb.vhd new file mode 100644 index 0000000..056b328 --- /dev/null +++ b/lib/SSRAM/src/ssram_frontend_wb.vhd @@ -0,0 +1,181 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +Library UNISIM; +use UNISIM.vcomponents.all; + +ENTITY ssram_frontend_wb IS + Generic + ( + latency : natural := 2; -- clock cycles + addr_width : natural := 20; + data_width : natural := 32; + parity_width : natural := 4 + ); + Port + ( + -- J-Bus domain + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + + -- Sync SRAM domain + ssram_clk_o : out std_logic; + ssram_clk_fb : in std_logic; + ssram_cke_n : out std_logic; + ssram_ce_n : out std_logic; + ssram_oe_n : out std_logic; + ssram_we_n : out std_logic; + ssram_adv : out std_logic; + ssram_mode : out std_logic; + ssram_zz : out std_logic; + ssram_a : out unsigned(addr_width-1 downto 0); + ssram_d : inout unsigned(data_width-1 downto 0); + ssram_dp : inout unsigned(parity_width-1 downto 0); + ssram_bw_n : out unsigned(3 downto 0) + ); +END ssram_frontend_wb; + +ARCHITECTURE behavior OF ssram_frontend_wb IS + + constant topad : time := 3 ns; + subtype ssram_d_t is unsigned(data_width+parity_width-1 downto 0); + type data_pipe_t is array (latency downto 0) of ssram_d_t; + + signal ssram_clk : std_logic; + signal dcm_locked : std_logic; + signal dcm_clk0 : std_logic; + signal dcm_clk1 : std_logic; + signal data_en : std_logic; + signal drive : std_logic; + signal vld_pipe : unsigned(latency downto 0); + signal drive_pipe : unsigned(latency downto 0); + signal data_pipe : data_pipe_t; + signal ssram_dout : ssram_d_t; + +begin + + SRDY_O <= CYC_I and dcm_locked; + ACK_O <= vld_pipe(vld_pipe'left); + DAT_O(data_width-1 downto 0) <= ssram_d; + + data_en <= CYC_I and STB_I; + ssram_dout <= "0000" & DAT_I(data_width-1 downto 0); + drive <= drive_pipe(drive_pipe'left); + + ssram_clk_o <= ssram_clk after topad; + ssram_cke_n <= not dcm_locked after topad; + ssram_oe_n <= not vld_pipe(vld_pipe'left-1) after topad; + +inst_clock_out : ODDR + generic map + ( + DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" + INIT => '0', -- Initial value for Q port ('1' or '0') + SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") + ) + port map ( + Q => ssram_clk, -- 1-bit DDR output + C => dcm_clk1, -- 1-bit clock input + CE => '1', -- 1-bit clock enable input + D1 => '1', -- 1-bit data input (positive edge) + D2 => '0', -- 1-bit data input (negative edge) + R => '0', -- 1-bit reset input + S => '0' -- 1-bit set input + ); + +ssram_bufg: bufg + port map + ( + o => dcm_clk1, + i => dcm_clk0 + ); + +inst_DCM_BASE_0 : DCM_BASE + generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00 + CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X + DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE + DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE + DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => open, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => dcm_locked, -- DCM LOCK status output + CLKFB => ssram_clk_fb, -- DCM clock feedback + CLKIN => CLK_I, -- Clock input (from IBUFG, BUFG or DCM) + RST => RST_I -- DCM asynchronous reset input + ); + + +data_valid_pipeline: + process(CLK_I) + begin + if rising_edge(CLK_I) then + if RST_I = '1' then + vld_pipe <= (others => '0'); + else + vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & (data_en and MRDY_I and not WE_I); + end if; + end if; + end process; + +data_out_pipeline: + process(CLK_I) + begin + if rising_edge(CLK_I) then + if RST_I = '1' then + ssram_ce_n <= '1' after topad; + ssram_we_n <= '1' after topad; + ssram_adv <= '0' after topad; + ssram_mode <= '0' after topad; + ssram_zz <= '1' after topad; + drive_pipe <= (others => '0'); + elsif dcm_locked = '1' then + ssram_ce_n <= not data_en after topad; + ssram_we_n <= not (WE_I and data_en) after topad; + ssram_adv <= '0' after topad; + ssram_mode <= '0' after topad; + ssram_zz <= '0' after topad; + ssram_a <= ADDR_I(addr_width-1 downto 0) after topad; + ssram_bw_n <= not SEL_I after topad; + drive_pipe <= drive_pipe(drive_pipe'left-1 downto 0) & (data_en and WE_I); + data_pipe <= data_pipe(data_pipe'left-1 downto 0) & ssram_dout; + end if; + end if; + end process; + + ssram_d <= data_pipe(data_pipe'left)(data_width-1 downto 0) after topad when drive = '1' else (others => 'Z') after topad; + ssram_dp <= data_pipe(data_pipe'left)(data_width+parity_width-1 downto data_width) after topad when drive = '1' else (others => 'Z') after topad; + +end behavior; diff --git a/lib/SSRAM/src/tb_ssram_frontend_wb.vhd b/lib/SSRAM/src/tb_ssram_frontend_wb.vhd new file mode 100644 index 0000000..86f1411 --- /dev/null +++ b/lib/SSRAM/src/tb_ssram_frontend_wb.vhd @@ -0,0 +1,457 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: testbench for system test using Xilinx ML-402 + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +USE work.package_utility.all; + +Library UNISIM; +use UNISIM.vcomponents.all; + +ENTITY tb_ssram_frontend_wb IS +END tb_ssram_frontend_wb; + +ARCHITECTURE behavior OF tb_ssram_frontend_wb IS + + constant CLK_PERIOD : time := 10 ns; + signal CLK_O : std_logic := '1'; + signal RST_O : std_logic := '1'; + signal CYC_O : std_logic := '0'; + signal STB_O : std_logic := '0'; + signal WE_O : std_logic := '0'; + signal SEL_O : unsigned(3 downto 0) := (others => '1'); + signal ACK_I : std_logic; + signal MRDY_O : std_logic := '1'; + signal SRDY_I : std_logic; + signal ADDR_O : unsigned(31 downto 0) := (others => '-'); + signal DAT_I : unsigned(31 downto 0); + signal DAT_O : unsigned(31 downto 0) := (others => '-'); + + SIGNAL ssram_d : unsigned (32 - 1 DOWNTO 0) := (OTHERS => 'Z'); + SIGNAL ssram_dp : unsigned (4 - 1 DOWNTO 0) := (OTHERS => 'Z'); + SIGNAL ssram_a : unsigned (20 - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ssram_clk : STD_LOGIC := '0'; + SIGNAL ssram_cke_n : STD_LOGIC; + SIGNAL ssram_adv : STD_LOGIC; + SIGNAL ssram_mode : STD_LOGIC; + SIGNAL ssram_bw_n : unsigned(3 downto 0); + SIGNAL ssram_we_n : STD_LOGIC; + SIGNAL ssram_oe_n : STD_LOGIC; + SIGNAL ssram_ce_n : STD_LOGIC; + SIGNAL ssram_zz : STD_LOGIC; + + SIGNAL ssram_clk_fb : STD_LOGIC; + + signal dout_rst : std_logic := '0'; + signal dout_reg : unsigned(31 downto 0); + signal dout_cnt : natural range 0 to 255; + +BEGIN + + ssram_clk_fb <= ssram_clk after 0.5 ns; + +inst_ssram_frontend_wb : entity work.ssram_frontend_wb + GENERIC MAP + ( + addr_width => 20, + data_width => 32, + parity_width => 4 + ) + PORT MAP + ( + -- J-Bus domain + RST_I => RST_O, + CLK_I => CLK_O, + CYC_I => CYC_O, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I, + SRDY_O => SRDY_I, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I, + + -- Sync SRAM domain + ssram_clk_o => ssram_clk, + ssram_clk_fb => ssram_clk_fb, + ssram_cke_n => ssram_cke_n, + ssram_ce_n => ssram_ce_n, + ssram_oe_n => ssram_oe_n, + ssram_we_n => ssram_we_n, + ssram_adv => ssram_adv, + ssram_mode => ssram_mode, + ssram_zz => ssram_zz, + ssram_a => ssram_a, + ssram_d => ssram_d, + ssram_dp => ssram_dp, + ssram_bw_n => ssram_bw_n + ); + +inst_ssram : entity work.cy7c1354 + -- PORT MAP Declarations + PORT MAP + ( + Dq => STD_LOGIC_VECTOR(ssram_d), -- Data I/O + Dpq => STD_LOGIC_VECTOR(ssram_dp), -- Data I/O + Addr => STD_LOGIC_VECTOR(ssram_a(19 downto 2)), -- Address + Mode => ssram_mode, -- Burst Mode + Clk => ssram_clk, -- Clk + CEN_n => ssram_cke_n, -- CEN# + AdvLd_n => ssram_adv, -- Adv/Ld# + Bwa_n => ssram_bw_n(0), -- Bwa# + Bwb_n => ssram_bw_n(1), -- BWb# + Bwc_n => ssram_bw_n(2), -- Bwc# + Bwd_n => ssram_bw_n(3), -- BWd# + Rw_n => ssram_we_n, -- RW# + Oe_n => ssram_oe_n, -- OE# + Ce1_n => ssram_ce_n, -- CE1# + Ce2 => '1', -- CE2 + Ce3_n => '0', -- CE3# + Zz => ssram_zz + ); + +read_register: + process(CLK_O) + begin + if rising_edge(CLK_O) then + if dout_rst = '1' then + dout_cnt <= 0; + elsif ACK_I = '1' and WE_O = '0' then + dout_reg <= DAT_I; + dout_cnt <= dout_cnt + 1; + end if; + end if; + end process; + +CLK_GEN: process + begin + wait for CLK_PERIOD/2; + CLK_O <= not CLK_O; + end process; + +STIMULUS: process + + begin + + wait for 5*CLK_PERIOD; + RST_O <= '0'; + + wait until rising_edge(CLK_O); + -- 8 single cycles + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '1'; + DAT_O <= X"1234_0000"; + ADDR_O <= X"0000_0000"; + + for i in 0 to 31 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + end loop; + + STB_O <= '0'; + wait until rising_edge(CLK_O); + CYC_O <= '0'; + + ------------------------------------------------------------ + wait for 3*CLK_PERIOD; + ------------------------------------------------------------ + + -- 8-word burst cycle + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '0'; + ADDR_O <= X"0000_0000"; + + for i in 0 to 31 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + STB_O <= '0'; + wait until rising_edge(CLK_O) and dout_cnt = 31; + CYC_O <= '0'; + + ------------------------------------------------------------ + wait for 3*CLK_PERIOD; + ------------------------------------------------------------ + + wait until rising_edge(CLK_O); + -- 1-word burst cycle + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '1'; + SEL_O <= "0011"; + ADDR_O <= X"0000_0010"; + DAT_O <= X"DEADBEEF"; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + wait until rising_edge(CLK_O); + CYC_O <= '0'; + + ------------------------------------------------------------ + wait for 3*CLK_PERIOD; + ------------------------------------------------------------ + + wait until rising_edge(CLK_O); + -- 1-word burst cycle + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '0'; + ADDR_O <= X"0000_0010"; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + wait until rising_edge(CLK_O) and ACK_I = '1'; + CYC_O <= '0'; + + ------------------------------------------------------------ + wait for 3*CLK_PERIOD; + ------------------------------------------------------------ + + -- 8-word burst cycle + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '0'; + ADDR_O <= X"0000_0000"; + + for i in 0 to 31 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + STB_O <= '0'; + wait until rising_edge(CLK_O) and dout_cnt = 31; + CYC_O <= '0'; + + ------------------------------------------------------------ + wait for 10*CLK_PERIOD; + ------------------------------------------------------------ + + + -- 8-word burst cycle + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '0'; + ADDR_O <= X"0000_0000"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + STB_O <= '0'; + wait until rising_edge(CLK_O) and dout_cnt = 7; + CYC_O <= '0'; + + + ------------------------------------------------------------ + wait for 10*CLK_PERIOD; + ------------------------------------------------------------ + + -- 8-word burst cycle + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '1'; + SEL_O <= "1111"; + DAT_O <= X"1111_0000"; + ADDR_O <= X"0000_0000"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + end loop; + + WE_O <= '0'; + ADDR_O <= X"0000_0000"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + STB_O <= '0'; + wait until rising_edge(CLK_O) and dout_cnt = 7; + CYC_O <= '0'; + + -- 8-word burst cycle + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '1'; + SEL_O <= "1111"; + DAT_O <= X"2222_0000"; + ADDR_O <= X"0000_0400"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + end loop; + + WE_O <= '0'; + ADDR_O <= X"0000_0400"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + STB_O <= '0'; + wait until rising_edge(CLK_O) and dout_cnt = 7; + CYC_O <= '0'; + + -- 8-word burst cycle + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '1'; + SEL_O <= "1111"; + DAT_O <= X"3333_0000"; + ADDR_O <= X"0000_0800"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + end loop; + + WE_O <= '0'; + ADDR_O <= X"0000_0800"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + STB_O <= '0'; + wait until rising_edge(CLK_O) and dout_cnt = 7; + CYC_O <= '0'; + + -- 8-word burst cycle + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '1'; + SEL_O <= "1111"; + DAT_O <= X"4444_0000"; + ADDR_O <= X"0000_0C00"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + end loop; + + WE_O <= '0'; + ADDR_O <= X"0000_0C00"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + STB_O <= '0'; + wait until rising_edge(CLK_O) and dout_cnt = 7; + CYC_O <= '0'; + + ------------------------------------------------------------ + wait for 10*CLK_PERIOD; + ------------------------------------------------------------ + + -- 8-word burst cycle + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '0'; + ADDR_O <= X"0000_0000"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + ADDR_O <= X"0000_0400"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + + ADDR_O <= X"0000_0800"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + + ADDR_O <= X"0000_0C00"; + + for i in 0 to 7 loop + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + end loop; + + STB_O <= '0'; + wait until rising_edge(CLK_O) and dout_cnt = 31; + CYC_O <= '0'; + + wait; + + end process; + +END; diff --git a/lib/VGA_ctrl/sim/ModelSim SE .lnk b/lib/VGA_ctrl/sim/ModelSim SE .lnk new file mode 100644 index 0000000000000000000000000000000000000000..6ece0338ba9194137022d20126be291e197c9b64 GIT binary patch literal 665 zcmah_K}Zx)82&~LB08)%!L|f#AqfS$>uNH)x6MkVU1zb-4g(`R+9imN1)6jdg}yhtjCAS^|Ns5--v58^dtVlSqP8#tAN-8_ z3&bcR^m50Ge%w~xt$M#C;!E3$qwUWM<}do4il5I?Mp1D!|6SjS{!EL|%GdL_l}Nn3 zjCgVl=RD-RbACYcMc`B~fx zW2nhc*N#O9IsNXv?4#N4Sh63zO^&*DAoP@0k{mfQn4Fx3$6Uk|#?XftlB|IU>xQ1X zc1pIIDEB0BJ>WSEcxn(Rqla^VimXH$61g3D5QXiS)^tVKF>8hr6T$Qerw4r%cA%m{ z9-H@DnDO6pg?uJMqO?|GFGDV=FwAIWyz1Iq4-rR2*>q|Z(A~W2Ou7Zzwv3z<;913~ zvA$TcX!x%%{#6ymDAF)cr2{72Fc<<8#1RZ2LsyD)$n{Se8pj(qFFz*AReJVRc$VAv yVSe&(?suv4+ThBM7Ip9W+ETT!|EVMXt^M^bE^U}|fBttaUvmyvzCm=FtbYN-OO;aq literal 0 HcmV?d00001 diff --git a/lib/misc/bbfifo.vhd b/lib/misc/bbfifo.vhd new file mode 100644 index 0000000..aa8799f --- /dev/null +++ b/lib/misc/bbfifo.vhd @@ -0,0 +1,123 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: Dual-ported register file with asynchrous read + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- +-- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $ +----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity bbfifo is + Generic + ( + depth : integer := 2; + data_width : integer := 8 + ); + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + re : in STD_LOGIC; + we : in STD_LOGIC; + ready : out STD_LOGIC; + avail : out STD_LOGIC; + din : in unsigned(data_width-1 downto 0); + dout : out unsigned(data_width-1 downto 0) + ); +end bbfifo; + +architecture Behavioral of bbfifo is + + type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0); + signal req : unsigned(0 to depth); + signal rdy : unsigned(1 to depth+1); + signal bucket_array : bucket_array_t; + signal ce_in : unsigned(1 to depth); + signal ce_out : unsigned(1 to depth); + +begin + + req(0) <= we; + rdy(depth+1) <= re; + ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0'; + avail <= req(depth); + bucket_array(0) <= din; + dout <= bucket_array(depth); + +gen_ce: + for i in 1 to depth generate + begin + process (rdy, req) + begin + ce_in(i) <= not req(i) and req(i-1); + end process; + end generate; + +gen_rdy: + for i in 1 to depth generate + begin + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then + rdy(i) <= '1'; + elsif req(i-1) = '1' then + rdy(i) <= rdy(i+1); + end if; + end if; + end process; + end generate; + +gen_req: + for i in 1 to depth generate + begin + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then + req(i) <= '0'; + elsif rdy(i+1) = '1' then + req(i) <= req(i-1); + end if; + end if; + end process; + end generate; + +gen_data: + for i in 1 to depth generate + begin + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then + bucket_array(i) <= (others => '0'); + elsif req(i-1) = '1' then + bucket_array(i) <= bucket_array(i-1); + end if; + end if; + end process; + end generate; + +end Behavioral; + diff --git a/lib/misc/gpio_wb.vhd b/lib/misc/gpio_wb.vhd new file mode 100644 index 0000000..4f358b1 --- /dev/null +++ b/lib/misc/gpio_wb.vhd @@ -0,0 +1,211 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +ENTITY gpio_wb IS + Port + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + + sys_gpo0 : out unsigned(31 downto 0); + sys_gpo1 : out unsigned(31 downto 0); + sys_gpi0 : in unsigned(31 downto 0); + sys_gpi1 : in unsigned(31 downto 0) + + ); +END gpio_wb; + +ARCHITECTURE behavior OF gpio_wb IS + + signal gpo0_reg : unsigned(31 downto 0); + signal gpo1_reg : unsigned(31 downto 0); + signal gpi0_reg : unsigned(31 downto 0); + signal gpi1_reg : unsigned(31 downto 0); + -- Signals to form an timer generating an interrupt every microsecond + subtype tick_usec_t is natural range 0 to 99; + signal tick_usec : tick_usec_t; + signal cnt_usec : unsigned(31 downto 0); + signal cnt_sec : unsigned(31 downto 0); + signal cnt_usec_preset : unsigned(31 downto 0); + signal cnt_sec_preset : unsigned(31 downto 0); + signal cnt_usec_en : std_logic; + signal cnt_usec_we : std_logic; + signal cnt_sec_en : std_logic; + signal cnt_sec_we : std_logic; + +begin + + SRDY_O <= CYC_I; + +------------------------------------------------------------------ +led_out: + process(CLK_I) + begin + if rising_edge(CLK_I) then + sys_gpo0 <= gpo0_reg; + sys_gpo1 <= gpo1_reg; + end if; + end process; + +------------------------------------------------------------------ +btn_ps2_in: + process(CLK_I) + begin + if rising_edge(CLK_I) then + gpi0_reg <= sys_gpi0; + gpi1_reg <= sys_gpi1; + end if; + end process; + +------------------------------------------------------------------ +registers_write: + process(CLK_I) + begin + if rising_edge(CLK_I) then + cnt_usec_we <= '0'; + cnt_sec_we <= '0'; + if RST_I = '1' then + gpo0_reg <= (others => '0'); + gpo1_reg <= (others => '0'); + elsif (STB_I and CYC_I and WE_I) = '1' then + case ADDR_I(5 downto 2) is + + when "0000" => + if SEL_I(0) = '1' then + gpo0_reg(7 downto 0) <= DAT_I(7 downto 0); + end if; + if SEL_I(1) = '1' then + gpo0_reg(15 downto 8) <= DAT_I(15 downto 8); + end if; + if SEL_I(2) = '1' then + gpo0_reg(23 downto 16) <= DAT_I(23 downto 16); + end if; + if SEL_I(3) = '1' then + gpo0_reg(31 downto 24) <= DAT_I(31 downto 24); + end if; + + when "0001" => + if SEL_I(0) = '1' then + gpo1_reg(7 downto 0) <= DAT_I(7 downto 0); + end if; + if SEL_I(1) = '1' then + gpo1_reg(15 downto 8) <= DAT_I(15 downto 8); + end if; + if SEL_I(2) = '1' then + gpo1_reg(23 downto 16) <= DAT_I(23 downto 16); + end if; + if SEL_I(3) = '1' then + gpo1_reg(31 downto 24) <= DAT_I(31 downto 24); + end if; + + when "0010" => + if SEL_I(3) = '1' then + cnt_usec_we <= '1'; + cnt_usec_preset <= DAT_I; + end if; + + when "0011" => + if SEL_I(3) = '1' then + cnt_sec_we <= '1'; + cnt_sec_preset <= DAT_I; + end if; + + when others => null; + end case; + end if; + end if; + end process; + +registers_read: + process(CLK_I) + begin + if rising_edge(CLK_I) then + ACK_O <= '0'; + if (STB_I and CYC_I) = '1' then + ACK_O <= not WE_I; + DAT_O <= (others => '0'); + case ADDR_I(5 downto 2) is + + when "0000" => + DAT_O <= gpi0_reg; + + when "0001" => + DAT_O <= gpi1_reg; + + when "0010" => + DAT_O <= cnt_usec; + + when "0011" => + DAT_O <= cnt_sec; + + when others => null; + end case; + end if; + end if; + end process; + +tick_usec_timer: + process(CLK_I) + begin + if rising_edge(CLK_I) then + cnt_usec_en <= '0'; + if RST_I = '1' then + tick_usec <= 0; + cnt_usec_en <= '0'; + elsif tick_usec = tick_usec_t'high then + tick_usec <= 0; + cnt_usec_en <= '1'; + else + tick_usec <= tick_usec + 1; + end if; + end if; + end process; + +cnt_usec_timer: + process(CLK_I) + begin + if rising_edge(CLK_I) then + cnt_sec_en <= '0'; + if RST_I = '1' then + cnt_usec <= (others => '0'); + cnt_sec_en <= '0'; + elsif cnt_usec_we = '1' then + cnt_usec <= cnt_usec_preset; + elsif cnt_usec_en = '1' then + if cnt_usec = to_unsigned(1E6 - 1, 32) then + cnt_usec <= (others => '0'); + cnt_sec_en <= '1'; + else + cnt_usec <= cnt_usec + 1; + end if; + end if; + end if; + end process; + +cnt_sec_timer: + process(CLK_I) + begin + if rising_edge(CLK_I) then + if RST_I = '1' then + cnt_sec <= (others => '0'); + elsif cnt_sec_we = '1' then + cnt_sec <= cnt_sec_preset; + elsif cnt_sec_en = '1' then + cnt_sec <= cnt_sec + 1; + end if; + end if; + end process; + +------------------------------------------------------------------ +end behavior; diff --git a/lib/misc/ram_sim.vhd b/lib/misc/ram_sim.vhd new file mode 100644 index 0000000..6d26672 --- /dev/null +++ b/lib/misc/ram_sim.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: The ROM file for use in your VHDL design +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + + +ENTITY ram IS + Generic + ( + word_addr_width : integer := 6 + ); + Port + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + we : in unsigned(3 downto 0); + addr : in unsigned(31 downto 0); + din : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); +END ram; + +ARCHITECTURE behavior OF ram IS + + constant depth : natural := 2**word_addr_width; + + type sram_t is array (0 to depth-1) of unsigned(31 downto 0); + + function sram_clear return sram_t is + + variable result : sram_t; + begin + for i in 0 to sram_t'length-1 loop + result(i) := (others => '0'); + end loop; + return result; + end sram_clear; + + signal sram : sram_t := sram_clear; + +BEGIN + + +SRAM_RW: + process(clk) + variable index : natural range 0 to depth-1; + begin + if rising_edge(clk) and ce = '1' then + index := to_integer(addr(word_addr_width+1 downto 2)); + if we(0) = '1' then + sram(index)(7 downto 0) <= din(7 downto 0); + end if; + if we(1) = '1' then + sram(index)(15 downto 8) <= din(15 downto 8); + end if; + if we(2) = '1' then + sram(index)(23 downto 16) <= din(23 downto 16); + end if; + if we(3) = '1' then + sram(index)(31 downto 24) <= din(31 downto 24); + end if; + dout <= sram(index); + end if; + end process; + +end behavior; diff --git a/lib/misc/ram_wb.vhd b/lib/misc/ram_wb.vhd new file mode 100644 index 0000000..2ebf242 --- /dev/null +++ b/lib/misc/ram_wb.vhd @@ -0,0 +1,80 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +ENTITY ram_wb IS + Port + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0) + ); +END ram_wb; + +ARCHITECTURE behavior OF ram_wb IS + + COMPONENT ram + GENERIC + ( + word_addr_width : integer + ); + PORT + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + we : in unsigned(3 downto 0); + addr : in unsigned(31 downto 0); + din : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); + END COMPONENT; + + signal data_en : std_logic; + signal we : unsigned(3 downto 0); + +begin + + we <= SEL_I and (3 downto 0 => WE_I); + + data_en <= CYC_I and STB_I and MRDY_I; + SRDY_O <= CYC_I; + +data_valid_register: + process(CLK_I) + begin + if rising_edge(CLK_I) then + if RST_I = '1' then + ACK_O <= '0'; + else + ACK_O <= data_en and not WE_I; + end if; + end if; + end process; + +inst_ram : ram + GENERIC MAP + ( + word_addr_width => 6 + ) + PORT MAP + ( + clk => CLK_I, + ce => data_en, + we => we, + addr => ADDR_I, + din => DAT_I, + dout => DAT_O + ); + + + +end behavior; diff --git a/lib/misc/rom_sim.vhd b/lib/misc/rom_sim.vhd new file mode 100644 index 0000000..98c0484 --- /dev/null +++ b/lib/misc/rom_sim.vhd @@ -0,0 +1,2082 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +ENTITY rom IS + Port + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + addr : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); +END rom; + +ARCHITECTURE data OF rom IS + + subtype word_t is unsigned(31 downto 0); + type word_array_t is array (0 to 2047) of word_t; + constant word_array : word_array_t := + ( + + X"3C1A1040", -- 00000000 + X"375A000C", -- 00000004 + X"409A6000", -- 00000008 + X"241A0000", -- 0000000C + X"409A6800", -- 00000010 + X"401A7800", -- 00000014 + X"00000000", -- 00000018 + X"409AF800", -- 0000001C + X"3C1ABFC0", -- 00000020 + X"275A01C4", -- 00000024 + X"03400008", -- 00000028 + X"00000000", -- 0000002C + X"00000000", -- 00000030 + X"00000000", -- 00000034 + X"00000000", -- 00000038 + X"00000000", -- 0000003C + X"00000000", -- 00000040 + X"00000000", -- 00000044 + X"00000000", -- 00000048 + X"00000000", -- 0000004C + X"00000000", -- 00000050 + X"00000000", -- 00000054 + X"00000000", -- 00000058 + X"00000000", -- 0000005C + X"00000000", -- 00000060 + X"00000000", -- 00000064 + X"00000000", -- 00000068 + X"00000000", -- 0000006C + X"00000000", -- 00000070 + X"00000000", -- 00000074 + X"00000000", -- 00000078 + X"00000000", -- 0000007C + X"00000000", -- 00000080 + X"00000000", -- 00000084 + X"00000000", -- 00000088 + X"00000000", -- 0000008C + X"00000000", -- 00000090 + X"00000000", -- 00000094 + X"00000000", -- 00000098 + X"00000000", -- 0000009C + X"00000000", -- 000000A0 + X"00000000", -- 000000A4 + X"00000000", -- 000000A8 + X"00000000", -- 000000AC + X"00000000", -- 000000B0 + X"00000000", -- 000000B4 + X"00000000", -- 000000B8 + X"00000000", -- 000000BC + X"00000000", -- 000000C0 + X"00000000", -- 000000C4 + X"00000000", -- 000000C8 + X"00000000", -- 000000CC + X"00000000", -- 000000D0 + X"00000000", -- 000000D4 + X"00000000", -- 000000D8 + X"00000000", -- 000000DC + X"00000000", -- 000000E0 + X"00000000", -- 000000E4 + X"00000000", -- 000000E8 + X"00000000", -- 000000EC + X"00000000", -- 000000F0 + X"00000000", -- 000000F4 + X"00000000", -- 000000F8 + X"00000000", -- 000000FC + X"00000000", -- 00000100 + X"00000000", -- 00000104 + X"00000000", -- 00000108 + X"00000000", -- 0000010C + X"00000000", -- 00000110 + X"00000000", -- 00000114 + X"00000000", -- 00000118 + X"00000000", -- 0000011C + X"00000000", -- 00000120 + X"00000000", -- 00000124 + X"00000000", -- 00000128 + X"00000000", -- 0000012C + X"00000000", -- 00000130 + X"00000000", -- 00000134 + X"00000000", -- 00000138 + X"00000000", -- 0000013C + X"00000000", -- 00000140 + X"00000000", -- 00000144 + X"00000000", -- 00000148 + X"00000000", -- 0000014C + X"00000000", -- 00000150 + X"00000000", -- 00000154 + X"00000000", -- 00000158 + X"00000000", -- 0000015C + X"00000000", -- 00000160 + X"00000000", -- 00000164 + X"00000000", -- 00000168 + X"00000000", -- 0000016C + X"00000000", -- 00000170 + X"00000000", -- 00000174 + X"00000000", -- 00000178 + X"00000000", -- 0000017C + X"401A6800", -- 00000180 + X"3C1BA000", -- 00000184 + X"277B0000", -- 00000188 + X"001AD082", -- 0000018C + X"335A000F", -- 00000190 + X"035BD025", -- 00000194 + X"AF7A0000", -- 00000198 + X"401A6800", -- 0000019C + X"00000000", -- 000001A0 + X"001AD202", -- 000001A4 + X"335A00FF", -- 000001A8 + X"1740FFFB", -- 000001AC + X"00000000", -- 000001B0 + X"401A7000", -- 000001B4 + X"00000000", -- 000001B8 + X"03400008", -- 000001BC + X"42000010", -- 000001C0 + X"3C1AA001", -- 000001C4 + X"275A0008", -- 000001C8 + X"241B000D", -- 000001CC + X"A35B0000", -- 000001D0 + X"3C1DBFD0", -- 000001D4 + X"27BDFFF0", -- 000001D8 + X"241A0005", -- 000001DC + X"1340009F", -- 000001E0 + X"241AFFFB", -- 000001E4 + X"1340009D", -- 000001E8 + X"241A0000", -- 000001EC + X"13400003", -- 000001F0 + X"00000000", -- 000001F4 + X"0BF00118", -- 000001F8 + X"00000000", -- 000001FC + X"241A0005", -- 00000200 + X"241B0006", -- 00000204 + X"135B0095", -- 00000208 + X"241AFFFB", -- 0000020C + X"135B0093", -- 00000210 + X"241A0000", -- 00000214 + X"135B0091", -- 00000218 + X"241A0006", -- 0000021C + X"135B0003", -- 00000220 + X"00000000", -- 00000224 + X"0BF00118", -- 00000228 + X"00000000", -- 0000022C + X"241AFFFB", -- 00000230 + X"0741008A", -- 00000234 + X"241A0005", -- 00000238 + X"07410002", -- 0000023C + X"00000000", -- 00000240 + X"0BF00118", -- 00000244 + X"241A0000", -- 00000248 + X"07410002", -- 0000024C + X"00000000", -- 00000250 + X"0BF00118", -- 00000254 + X"241AFFFB", -- 00000258 + X"1F400080", -- 0000025C + X"241A0000", -- 00000260 + X"1F40007E", -- 00000264 + X"241A0005", -- 00000268 + X"1F400002", -- 0000026C + X"00000000", -- 00000270 + X"0BF00118", -- 00000274 + X"241A0005", -- 00000278 + X"1B400078", -- 0000027C + X"241A0000", -- 00000280 + X"1B400002", -- 00000284 + X"00000000", -- 00000288 + X"0BF00118", -- 0000028C + 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X"544F4F42", -- 00001638 + X"00000020", -- 0000163C + X"41524453", -- 00001640 + X"654D204D", -- 00001644 + X"79726F6D", -- 00001648 + X"73655420", -- 0000164C + X"000A0D74", -- 00001650 + X"74697257", -- 00001654 + X"38282065", -- 00001658 + X"7469422D", -- 0000165C + X"63636120", -- 00001660 + X"29737365", -- 00001664 + X"002E2E2E", -- 00001668 + X"656E6F64", -- 0000166C + X"00000A0D", -- 00001670 + X"69726556", -- 00001674 + X"28207966", -- 00001678 + X"69422D38", -- 0000167C + X"63612074", -- 00001680 + X"73736563", -- 00001684 + X"2E2E2E29", -- 00001688 + X"00000000", -- 0000168C + X"6C696166", -- 00001690 + X"0A0D6465", -- 00001694 + X"00000000", -- 00001698 + X"73736170", -- 0000169C + X"0A0D6465", -- 000016A0 + X"00000000", -- 000016A4 + X"74697257", -- 000016A8 + X"31282065", -- 000016AC + X"69422D36", -- 000016B0 + X"63612074", -- 000016B4 + X"73736563", -- 000016B8 + X"2E2E2E29", -- 000016BC + X"00000000", -- 000016C0 + X"69726556", -- 000016C4 + X"28207966", -- 000016C8 + X"422D3631", -- 000016CC + X"61207469", -- 000016D0 + X"73656363", -- 000016D4 + X"2E2E2973", -- 000016D8 + X"0000002E", -- 000016DC + X"74697257", -- 000016E0 + X"33282065", -- 000016E4 + X"69422D32", -- 000016E8 + X"63612074", -- 000016EC + X"73736563", -- 000016F0 + X"2E2E2E29", -- 000016F4 + X"00000000", -- 000016F8 + X"69726556", -- 000016FC + X"28207966", -- 00001700 + X"422D3233", -- 00001704 + X"61207469", -- 00001708 + X"73656363", -- 0000170C + X"2E2E2973", -- 00001710 + X"0000002E", -- 00001714 + X"206F7420", -- 00001718 + X"00000000", -- 0000171C + X"00000A0D", -- 00001720 + X"00000000", -- 00001724 + X"00000000", -- 00001728 + X"00000000", -- 0000172C + X"00000000", -- 00001730 + X"00000000", -- 00001734 + X"00000000", -- 00001738 + X"00000000", -- 0000173C + X"00000000", -- 00001740 + X"00000000", -- 00001744 + X"00000000", -- 00001748 + X"00000000", -- 0000174C + X"00000000", -- 00001750 + X"00000000", -- 00001754 + X"00000000", -- 00001758 + X"00000000", -- 0000175C + X"00000000", -- 00001760 + X"00000000", -- 00001764 + X"00000000", -- 00001768 + X"00000000", -- 0000176C + X"00000000", -- 00001770 + X"00000000", -- 00001774 + X"00000000", -- 00001778 + X"00000000", -- 0000177C + X"00000000", -- 00001780 + X"00000000", -- 00001784 + X"00000000", -- 00001788 + X"00000000", -- 0000178C + X"00000000", -- 00001790 + X"00000000", -- 00001794 + X"00000000", -- 00001798 + X"00000000", -- 0000179C + X"00000000", -- 000017A0 + X"00000000", -- 000017A4 + X"00000000", -- 000017A8 + X"00000000", -- 000017AC + X"00000000", -- 000017B0 + X"00000000", -- 000017B4 + X"00000000", -- 000017B8 + X"00000000", -- 000017BC + X"00000000", -- 000017C0 + X"00000000", -- 000017C4 + X"00000000", -- 000017C8 + X"00000000", -- 000017CC + X"00000000", -- 000017D0 + X"00000000", -- 000017D4 + X"00000000", -- 000017D8 + X"00000000", -- 000017DC + X"00000000", -- 000017E0 + X"00000000", -- 000017E4 + X"00000000", -- 000017E8 + X"00000000", -- 000017EC + X"00000000", -- 000017F0 + X"00000000", -- 000017F4 + X"00000000", -- 000017F8 + X"00000000", -- 000017FC + X"00000000", -- 00001800 + X"00000000", -- 00001804 + X"00000000", -- 00001808 + X"00000000", -- 0000180C + X"00000000", -- 00001810 + X"00000000", -- 00001814 + X"00000000", -- 00001818 + X"00000000", -- 0000181C + X"00000000", -- 00001820 + X"00000000", -- 00001824 + X"00000000", -- 00001828 + X"00000000", -- 0000182C + X"00000000", -- 00001830 + X"00000000", -- 00001834 + X"00000000", -- 00001838 + X"00000000", -- 0000183C + X"00000000", -- 00001840 + X"00000000", -- 00001844 + X"00000000", -- 00001848 + X"00000000", -- 0000184C + X"00000000", -- 00001850 + X"00000000", -- 00001854 + X"00000000", -- 00001858 + X"00000000", -- 0000185C + X"00000000", -- 00001860 + X"00000000", -- 00001864 + X"00000000", -- 00001868 + X"00000000", -- 0000186C + X"00000000", -- 00001870 + X"00000000", -- 00001874 + X"00000000", -- 00001878 + X"00000000", -- 0000187C + X"00000000", -- 00001880 + X"00000000", -- 00001884 + X"00000000", -- 00001888 + X"00000000", -- 0000188C + X"00000000", -- 00001890 + X"00000000", -- 00001894 + X"00000000", -- 00001898 + X"00000000", -- 0000189C + X"00000000", -- 000018A0 + X"00000000", -- 000018A4 + X"00000000", -- 000018A8 + X"00000000", -- 000018AC + X"00000000", -- 000018B0 + X"00000000", -- 000018B4 + X"00000000", -- 000018B8 + X"00000000", -- 000018BC + X"00000000", -- 000018C0 + X"00000000", -- 000018C4 + X"00000000", -- 000018C8 + X"00000000", -- 000018CC + X"00000000", -- 000018D0 + X"00000000", -- 000018D4 + X"00000000", -- 000018D8 + X"00000000", -- 000018DC + X"00000000", -- 000018E0 + X"00000000", -- 000018E4 + X"00000000", -- 000018E8 + X"00000000", -- 000018EC + X"00000000", -- 000018F0 + X"00000000", -- 000018F4 + X"00000000", -- 000018F8 + X"00000000", -- 000018FC + X"00000000", -- 00001900 + X"00000000", -- 00001904 + X"00000000", -- 00001908 + X"00000000", -- 0000190C + X"00000000", -- 00001910 + X"00000000", -- 00001914 + X"00000000", -- 00001918 + X"00000000", -- 0000191C + X"00000000", -- 00001920 + X"00000000", -- 00001924 + X"00000000", -- 00001928 + X"00000000", -- 0000192C + X"00000000", -- 00001930 + X"00000000", -- 00001934 + X"00000000", -- 00001938 + X"00000000", -- 0000193C + X"00000000", -- 00001940 + X"00000000", -- 00001944 + X"00000000", -- 00001948 + X"00000000", -- 0000194C + X"00000000", -- 00001950 + X"00000000", -- 00001954 + X"00000000", -- 00001958 + X"00000000", -- 0000195C + X"00000000", -- 00001960 + X"00000000", -- 00001964 + X"00000000", -- 00001968 + X"00000000", -- 0000196C + X"00000000", -- 00001970 + X"00000000", -- 00001974 + X"00000000", -- 00001978 + X"00000000", -- 0000197C + X"00000000", -- 00001980 + X"00000000", -- 00001984 + X"00000000", -- 00001988 + X"00000000", -- 0000198C + X"00000000", -- 00001990 + X"00000000", -- 00001994 + X"00000000", -- 00001998 + X"00000000", -- 0000199C + X"00000000", -- 000019A0 + X"00000000", -- 000019A4 + X"00000000", -- 000019A8 + X"00000000", -- 000019AC + X"00000000", -- 000019B0 + X"00000000", -- 000019B4 + X"00000000", -- 000019B8 + X"00000000", -- 000019BC + X"00000000", -- 000019C0 + X"00000000", -- 000019C4 + X"00000000", -- 000019C8 + X"00000000", -- 000019CC + X"00000000", -- 000019D0 + X"00000000", -- 000019D4 + X"00000000", -- 000019D8 + X"00000000", -- 000019DC + X"00000000", -- 000019E0 + X"00000000", -- 000019E4 + X"00000000", -- 000019E8 + X"00000000", -- 000019EC + X"00000000", -- 000019F0 + X"00000000", -- 000019F4 + X"00000000", -- 000019F8 + X"00000000", -- 000019FC + X"00000000", -- 00001A00 + X"00000000", -- 00001A04 + X"00000000", -- 00001A08 + X"00000000", -- 00001A0C + X"00000000", -- 00001A10 + X"00000000", -- 00001A14 + X"00000000", -- 00001A18 + X"00000000", -- 00001A1C + X"00000000", -- 00001A20 + X"00000000", -- 00001A24 + X"00000000", -- 00001A28 + X"00000000", -- 00001A2C + X"00000000", -- 00001A30 + X"00000000", -- 00001A34 + X"00000000", -- 00001A38 + X"00000000", -- 00001A3C + X"00000000", -- 00001A40 + X"00000000", -- 00001A44 + X"00000000", -- 00001A48 + X"00000000", -- 00001A4C + X"00000000", -- 00001A50 + X"00000000", -- 00001A54 + X"00000000", -- 00001A58 + X"00000000", -- 00001A5C + X"00000000", -- 00001A60 + X"00000000", -- 00001A64 + X"00000000", -- 00001A68 + X"00000000", -- 00001A6C + X"00000000", -- 00001A70 + X"00000000", -- 00001A74 + X"00000000", -- 00001A78 + X"00000000", -- 00001A7C + X"00000000", -- 00001A80 + X"00000000", -- 00001A84 + X"00000000", -- 00001A88 + X"00000000", -- 00001A8C + X"00000000", -- 00001A90 + X"00000000", -- 00001A94 + X"00000000", -- 00001A98 + X"00000000", -- 00001A9C + X"00000000", -- 00001AA0 + X"00000000", -- 00001AA4 + X"00000000", -- 00001AA8 + X"00000000", -- 00001AAC + X"00000000", -- 00001AB0 + X"00000000", -- 00001AB4 + X"00000000", -- 00001AB8 + X"00000000", -- 00001ABC + X"00000000", -- 00001AC0 + X"00000000", -- 00001AC4 + X"00000000", -- 00001AC8 + X"00000000", -- 00001ACC + X"00000000", -- 00001AD0 + X"00000000", -- 00001AD4 + X"00000000", -- 00001AD8 + X"00000000", -- 00001ADC + X"00000000", -- 00001AE0 + X"00000000", -- 00001AE4 + X"00000000", -- 00001AE8 + X"00000000", -- 00001AEC + X"00000000", -- 00001AF0 + X"00000000", -- 00001AF4 + X"00000000", -- 00001AF8 + X"00000000", -- 00001AFC + X"00000000", -- 00001B00 + X"00000000", -- 00001B04 + X"00000000", -- 00001B08 + X"00000000", -- 00001B0C + X"00000000", -- 00001B10 + X"00000000", -- 00001B14 + X"00000000", -- 00001B18 + X"00000000", -- 00001B1C + X"00000000", -- 00001B20 + X"00000000", -- 00001B24 + X"00000000", -- 00001B28 + X"00000000", -- 00001B2C + X"00000000", -- 00001B30 + X"00000000", -- 00001B34 + X"00000000", -- 00001B38 + X"00000000", -- 00001B3C + X"00000000", -- 00001B40 + X"00000000", -- 00001B44 + X"00000000", -- 00001B48 + X"00000000", -- 00001B4C + X"00000000", -- 00001B50 + X"00000000", -- 00001B54 + X"00000000", -- 00001B58 + X"00000000", -- 00001B5C + X"00000000", -- 00001B60 + X"00000000", -- 00001B64 + X"00000000", -- 00001B68 + X"00000000", -- 00001B6C + X"00000000", -- 00001B70 + X"00000000", -- 00001B74 + X"00000000", -- 00001B78 + X"00000000", -- 00001B7C + X"00000000", -- 00001B80 + X"00000000", -- 00001B84 + X"00000000", -- 00001B88 + X"00000000", -- 00001B8C + X"00000000", -- 00001B90 + X"00000000", -- 00001B94 + X"00000000", -- 00001B98 + X"00000000", -- 00001B9C + X"00000000", -- 00001BA0 + X"00000000", -- 00001BA4 + X"00000000", -- 00001BA8 + X"00000000", -- 00001BAC + X"00000000", -- 00001BB0 + X"00000000", -- 00001BB4 + X"00000000", -- 00001BB8 + X"00000000", -- 00001BBC + X"00000000", -- 00001BC0 + X"00000000", -- 00001BC4 + X"00000000", -- 00001BC8 + X"00000000", -- 00001BCC + X"00000000", -- 00001BD0 + X"00000000", -- 00001BD4 + X"00000000", -- 00001BD8 + X"00000000", -- 00001BDC + X"00000000", -- 00001BE0 + X"00000000", -- 00001BE4 + X"00000000", -- 00001BE8 + X"00000000", -- 00001BEC + X"00000000", -- 00001BF0 + X"00000000", -- 00001BF4 + X"00000000", -- 00001BF8 + X"00000000", -- 00001BFC + X"00000000", -- 00001C00 + X"00000000", -- 00001C04 + X"00000000", -- 00001C08 + X"00000000", -- 00001C0C + X"00000000", -- 00001C10 + X"00000000", -- 00001C14 + X"00000000", -- 00001C18 + X"00000000", -- 00001C1C + X"00000000", -- 00001C20 + X"00000000", -- 00001C24 + X"00000000", -- 00001C28 + X"00000000", -- 00001C2C + X"00000000", -- 00001C30 + X"00000000", -- 00001C34 + X"00000000", -- 00001C38 + X"00000000", -- 00001C3C + X"00000000", -- 00001C40 + X"00000000", -- 00001C44 + X"00000000", -- 00001C48 + X"00000000", -- 00001C4C + X"00000000", -- 00001C50 + X"00000000", -- 00001C54 + X"00000000", -- 00001C58 + X"00000000", -- 00001C5C + X"00000000", -- 00001C60 + X"00000000", -- 00001C64 + X"00000000", -- 00001C68 + X"00000000", -- 00001C6C + X"00000000", -- 00001C70 + X"00000000", -- 00001C74 + X"00000000", -- 00001C78 + X"00000000", -- 00001C7C + X"00000000", -- 00001C80 + X"00000000", -- 00001C84 + X"00000000", -- 00001C88 + X"00000000", -- 00001C8C + X"00000000", -- 00001C90 + X"00000000", -- 00001C94 + X"00000000", -- 00001C98 + X"00000000", -- 00001C9C + X"00000000", -- 00001CA0 + X"00000000", -- 00001CA4 + X"00000000", -- 00001CA8 + X"00000000", -- 00001CAC + X"00000000", -- 00001CB0 + X"00000000", -- 00001CB4 + X"00000000", -- 00001CB8 + X"00000000", -- 00001CBC + X"00000000", -- 00001CC0 + X"00000000", -- 00001CC4 + X"00000000", -- 00001CC8 + X"00000000", -- 00001CCC + X"00000000", -- 00001CD0 + X"00000000", -- 00001CD4 + X"00000000", -- 00001CD8 + X"00000000", -- 00001CDC + X"00000000", -- 00001CE0 + X"00000000", -- 00001CE4 + X"00000000", -- 00001CE8 + X"00000000", -- 00001CEC + X"00000000", -- 00001CF0 + X"00000000", -- 00001CF4 + X"00000000", -- 00001CF8 + X"00000000", -- 00001CFC + X"00000000", -- 00001D00 + X"00000000", -- 00001D04 + X"00000000", -- 00001D08 + X"00000000", -- 00001D0C + X"00000000", -- 00001D10 + X"00000000", -- 00001D14 + X"00000000", -- 00001D18 + X"00000000", -- 00001D1C + X"00000000", -- 00001D20 + X"00000000", -- 00001D24 + X"00000000", -- 00001D28 + X"00000000", -- 00001D2C + X"00000000", -- 00001D30 + X"00000000", -- 00001D34 + X"00000000", -- 00001D38 + X"00000000", -- 00001D3C + X"00000000", -- 00001D40 + X"00000000", -- 00001D44 + X"00000000", -- 00001D48 + X"00000000", -- 00001D4C + X"00000000", -- 00001D50 + X"00000000", -- 00001D54 + X"00000000", -- 00001D58 + X"00000000", -- 00001D5C + X"00000000", -- 00001D60 + X"00000000", -- 00001D64 + X"00000000", -- 00001D68 + X"00000000", -- 00001D6C + X"00000000", -- 00001D70 + X"00000000", -- 00001D74 + X"00000000", -- 00001D78 + X"00000000", -- 00001D7C + X"00000000", -- 00001D80 + X"00000000", -- 00001D84 + X"00000000", -- 00001D88 + X"00000000", -- 00001D8C + X"00000000", -- 00001D90 + X"00000000", -- 00001D94 + X"00000000", -- 00001D98 + X"00000000", -- 00001D9C + X"00000000", -- 00001DA0 + X"00000000", -- 00001DA4 + X"00000000", -- 00001DA8 + X"00000000", -- 00001DAC + X"00000000", -- 00001DB0 + X"00000000", -- 00001DB4 + X"00000000", -- 00001DB8 + X"00000000", -- 00001DBC + X"00000000", -- 00001DC0 + X"00000000", -- 00001DC4 + X"00000000", -- 00001DC8 + X"00000000", -- 00001DCC + X"00000000", -- 00001DD0 + X"00000000", -- 00001DD4 + X"00000000", -- 00001DD8 + X"00000000", -- 00001DDC + X"00000000", -- 00001DE0 + X"00000000", -- 00001DE4 + X"00000000", -- 00001DE8 + X"00000000", -- 00001DEC + X"00000000", -- 00001DF0 + X"00000000", -- 00001DF4 + X"00000000", -- 00001DF8 + X"00000000", -- 00001DFC + X"00000000", -- 00001E00 + X"00000000", -- 00001E04 + X"00000000", -- 00001E08 + X"00000000", -- 00001E0C + X"00000000", -- 00001E10 + X"00000000", -- 00001E14 + X"00000000", -- 00001E18 + X"00000000", -- 00001E1C + X"00000000", -- 00001E20 + X"00000000", -- 00001E24 + X"00000000", -- 00001E28 + X"00000000", -- 00001E2C + X"00000000", -- 00001E30 + X"00000000", -- 00001E34 + X"00000000", -- 00001E38 + X"00000000", -- 00001E3C + X"00000000", -- 00001E40 + X"00000000", -- 00001E44 + X"00000000", -- 00001E48 + X"00000000", -- 00001E4C + X"00000000", -- 00001E50 + X"00000000", -- 00001E54 + X"00000000", -- 00001E58 + X"00000000", -- 00001E5C + X"00000000", -- 00001E60 + X"00000000", -- 00001E64 + X"00000000", -- 00001E68 + X"00000000", -- 00001E6C + X"00000000", -- 00001E70 + X"00000000", -- 00001E74 + X"00000000", -- 00001E78 + X"00000000", -- 00001E7C + X"00000000", -- 00001E80 + X"00000000", -- 00001E84 + X"00000000", -- 00001E88 + X"00000000", -- 00001E8C + X"00000000", -- 00001E90 + X"00000000", -- 00001E94 + X"00000000", -- 00001E98 + X"00000000", -- 00001E9C + X"00000000", -- 00001EA0 + X"00000000", -- 00001EA4 + X"00000000", -- 00001EA8 + X"00000000", -- 00001EAC + X"00000000", -- 00001EB0 + X"00000000", -- 00001EB4 + X"00000000", -- 00001EB8 + X"00000000", -- 00001EBC + X"00000000", -- 00001EC0 + X"00000000", -- 00001EC4 + X"00000000", -- 00001EC8 + X"00000000", -- 00001ECC + X"00000000", -- 00001ED0 + X"00000000", -- 00001ED4 + X"00000000", -- 00001ED8 + X"00000000", -- 00001EDC + X"00000000", -- 00001EE0 + X"00000000", -- 00001EE4 + X"00000000", -- 00001EE8 + X"00000000", -- 00001EEC + X"00000000", -- 00001EF0 + X"00000000", -- 00001EF4 + X"00000000", -- 00001EF8 + X"00000000", -- 00001EFC + X"00000000", -- 00001F00 + X"00000000", -- 00001F04 + X"00000000", -- 00001F08 + X"00000000", -- 00001F0C + X"00000000", -- 00001F10 + X"00000000", -- 00001F14 + X"00000000", -- 00001F18 + X"00000000", -- 00001F1C + X"00000000", -- 00001F20 + X"00000000", -- 00001F24 + X"00000000", -- 00001F28 + X"00000000", -- 00001F2C + X"00000000", -- 00001F30 + X"00000000", -- 00001F34 + X"00000000", -- 00001F38 + X"00000000", -- 00001F3C + X"00000000", -- 00001F40 + X"00000000", -- 00001F44 + X"00000000", -- 00001F48 + X"00000000", -- 00001F4C + X"00000000", -- 00001F50 + X"00000000", -- 00001F54 + X"00000000", -- 00001F58 + X"00000000", -- 00001F5C + X"00000000", -- 00001F60 + X"00000000", -- 00001F64 + X"00000000", -- 00001F68 + X"00000000", -- 00001F6C + X"00000000", -- 00001F70 + X"00000000", -- 00001F74 + X"00000000", -- 00001F78 + X"00000000", -- 00001F7C + X"00000000", -- 00001F80 + X"00000000", -- 00001F84 + X"00000000", -- 00001F88 + X"00000000", -- 00001F8C + X"00000000", -- 00001F90 + X"00000000", -- 00001F94 + X"00000000", -- 00001F98 + X"00000000", -- 00001F9C + X"00000000", -- 00001FA0 + X"00000000", -- 00001FA4 + X"00000000", -- 00001FA8 + X"00000000", -- 00001FAC + X"00000000", -- 00001FB0 + X"00000000", -- 00001FB4 + X"00000000", -- 00001FB8 + X"00000000", -- 00001FBC + X"00000000", -- 00001FC0 + X"00000000", -- 00001FC4 + X"00000000", -- 00001FC8 + X"00000000", -- 00001FCC + X"00000000", -- 00001FD0 + X"00000000", -- 00001FD4 + X"00000000", -- 00001FD8 + X"00000000", -- 00001FDC + X"00000000", -- 00001FE0 + X"00000000", -- 00001FE4 + X"00000000", -- 00001FE8 + X"00000000", -- 00001FEC + X"00000000", -- 00001FF0 + X"00000000", -- 00001FF4 + X"00000000", -- 00001FF8 + X"00000000" -- 00001FFC + ); + +begin + +PROM_READ: + process(clk) + begin + if rising_edge(clk) and ce = '1' then + dout <= word_array(to_integer(addr(12 downto 2))); + end if; + end process; + +end data; diff --git a/lib/misc/rom_wb.vhd b/lib/misc/rom_wb.vhd new file mode 100644 index 0000000..9fa3715 --- /dev/null +++ b/lib/misc/rom_wb.vhd @@ -0,0 +1,61 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +ENTITY rom_wb IS + Port + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + SRDY_O : out STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0) + ); +END rom_wb; + +ARCHITECTURE behavior OF rom_wb IS + + COMPONENT rom + PORT + ( + clk : in STD_LOGIC; + ce : in STD_LOGIC; + addr : in unsigned(31 downto 0); + dout : out unsigned(31 downto 0) + ); + END COMPONENT; + + signal data_en : std_logic; + +begin + + data_en <= CYC_I and STB_I and MRDY_I; + SRDY_O <= CYC_I; + +data_valid_register: + process(CLK_I) + begin + if rising_edge(CLK_I) then + if RST_I = '1' then + ACK_O <= '0'; + else + ACK_O <= data_en; -- and not WE_I; + end if; + end if; + end process; + +inst_rom : rom + PORT MAP + ( + clk => CLK_I, + ce => data_en, + addr => ADDR_I, + dout => DAT_O + ); + + +end behavior; diff --git a/lib/misc/sim/ModelSim SE .lnk b/lib/misc/sim/ModelSim SE .lnk new file mode 100644 index 0000000000000000000000000000000000000000..2b9e5b55cd601bb9f8f944f267e1d78d2623cad9 GIT binary patch literal 657 zcmah_K}Z`x6n$$fc<3SG7BmzZMOtVfiP1`uTTHD;lP0L3hXqZu+c@H8OR^>kMUUD` zDR@&XVh`=D6zZ`}K@{;M9@L8tzG5qJNu_(>@~hT-`!F0=B87rICu?lMa7-WX?oxPBPP5X$4z(;3azyv zn22fDRc_XYE+-F0%d5@E45bH#;`7|P4-Xn~_Vr8T^-3bzqN}XRpa=_jViqPpgL|!b zT34t>{s=Ep=|}y^k@>DbIDwwJMm6$FB%+@Tsga_B&dzDr#2h9uj$Q;1W)Aq6*Zfo? zmsG2WLU$M)uFjdOQ-MGM-RuKYBqehozK6aiewdbSOqYZiFlK2ntkfOreh%+bzM9=2r)}^-*8C_}{sF#SLKnF4?N9UI9sKl`sGR literal 0 HcmV?d00001 diff --git a/lib/misc/sim/tb_bbfifo.fdo b/lib/misc/sim/tb_bbfifo.fdo new file mode 100644 index 0000000..5a23c76 --- /dev/null +++ b/lib/misc/sim/tb_bbfifo.fdo @@ -0,0 +1,14 @@ +## NOTE: Do not edit this file. +## + +vlib work +vcom -explicit -93 "../bbfifo.vhd" +vcom -explicit -93 "../tb_bbfifo.vhd" + +#restart -force +vsim -t 1ps -lib work tb_bbfifo +do {tb_bbfifo.wdo} +view wave +view structure +view signals +run 1us diff --git a/lib/misc/sim/tb_bbfifo.wdo b/lib/misc/sim/tb_bbfifo.wdo new file mode 100644 index 0000000..06b107e --- /dev/null +++ b/lib/misc/sim/tb_bbfifo.wdo @@ -0,0 +1,31 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_bbfifo/rst +add wave -noupdate -format Logic /tb_bbfifo/clk +add wave -noupdate -format Logic /tb_bbfifo/re +add wave -noupdate -format Logic /tb_bbfifo/we +add wave -noupdate -format Logic /tb_bbfifo/ready +add wave -noupdate -format Logic /tb_bbfifo/avail +add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din +add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout +add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/req +add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/rdy +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_bbfifo/inst_bbfifo/bucket_array +add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_in +add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_out +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {170000 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {76738 ps} {299465 ps} diff --git a/lib/misc/sim/tb_ram_wb.fdo b/lib/misc/sim/tb_ram_wb.fdo new file mode 100644 index 0000000..1174591 --- /dev/null +++ b/lib/misc/sim/tb_ram_wb.fdo @@ -0,0 +1,16 @@ +## NOTE: Do not edit this file. +## +vlib work + +# Top and TB +vcom -explicit -93 "../ram_sim.vhd" +vcom -explicit -93 "../ram_wb.vhd" +vcom -explicit -93 "../tb_ram_wb.vhd" + +vsim -t 1ps -lib work tb_ram_wb +do {tb_ram_wb.wdo} +view wave +view structure +view signals +run 1.5us + \ No newline at end of file diff --git a/lib/misc/sim/tb_ram_wb.wdo b/lib/misc/sim/tb_ram_wb.wdo new file mode 100644 index 0000000..2cdca8e --- /dev/null +++ b/lib/misc/sim/tb_ram_wb.wdo @@ -0,0 +1,32 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_ram_wb/clk_o +add wave -noupdate -format Logic /tb_ram_wb/rst_o +add wave -noupdate -format Logic /tb_ram_wb/cyc_o +add wave -noupdate -format Logic /tb_ram_wb/stb_o +add wave -noupdate -format Logic /tb_ram_wb/we_o +add wave -noupdate -format Literal /tb_ram_wb/sel_o +add wave -noupdate -format Logic /tb_ram_wb/ack_i +add wave -noupdate -format Logic /tb_ram_wb/mrdy_o +add wave -noupdate -format Logic /tb_ram_wb/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o +add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg +add wave -noupdate -format Literal /tb_ram_wb/dout_cnt +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {950000 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {1575 ns} diff --git a/lib/misc/sim/tb_rom_wb.fdo b/lib/misc/sim/tb_rom_wb.fdo new file mode 100644 index 0000000..e8732f0 --- /dev/null +++ b/lib/misc/sim/tb_rom_wb.fdo @@ -0,0 +1,16 @@ +## NOTE: Do not edit this file. +## +vlib work + +# Top and TB +vcom -explicit -93 "../rom_sim.vhd" +vcom -explicit -93 "../rom_wb.vhd" +vcom -explicit -93 "../tb_rom_wb.vhd" + +vsim -t 1ps -lib work tb_rom_wb +do {tb_rom_wb.wdo} +view wave +view structure +view signals +run 1us + \ No newline at end of file diff --git a/lib/misc/sim/tb_rom_wb.wdo b/lib/misc/sim/tb_rom_wb.wdo new file mode 100644 index 0000000..b8663ed --- /dev/null +++ b/lib/misc/sim/tb_rom_wb.wdo @@ -0,0 +1,29 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_rom_wb/clk_o +add wave -noupdate -format Logic /tb_rom_wb/rst_o +add wave -noupdate -format Logic /tb_rom_wb/cyc_o +add wave -noupdate -format Logic /tb_rom_wb/stb_o +add wave -noupdate -format Logic /tb_rom_wb/ack_i +add wave -noupdate -format Logic /tb_rom_wb/mrdy_o +add wave -noupdate -format Logic /tb_rom_wb/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dout_reg +add wave -noupdate -format Literal /tb_rom_wb/dout_cnt +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {796036 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {1050 ns} diff --git a/lib/misc/tb_bbfifo.vhd b/lib/misc/tb_bbfifo.vhd new file mode 100644 index 0000000..95fa7b9 --- /dev/null +++ b/lib/misc/tb_bbfifo.vhd @@ -0,0 +1,136 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: cpu_embedded using cpu_core and rom +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity tb_bbfifo is +end; + +architecture behave of tb_bbfifo is + + -- Number of user data words for simulation + constant CLK_PERIOD : time := 10 ns; + + signal rst : std_logic := '1'; + signal clk : std_logic := '1'; + signal re : std_logic := '0'; + signal we : std_logic := '0'; + signal ready : std_logic; + signal avail : std_logic; + signal din : unsigned(7 downto 0) := (others => '0'); + signal dout : unsigned(7 downto 0); + signal dout_reg : unsigned(7 downto 0); + + +begin + +inst_bbfifo : entity work.bbfifo + GENERIC MAP + ( + depth => 4, + data_width => 8 + ) + PORT MAP + ( + rst => rst, + clk => clk, + re => re, + we => we, + ready => ready, + avail => avail, + din => din, + dout => dout + ); + + +CLK_GEN: process + begin + wait for CLK_PERIOD/2; + clk <= not clk; + end process; + +RE_GEN: process + begin + wait for 2*CLK_PERIOD; + wait until rising_edge(clk) and avail = '1'; + re <= '0'; + dout_reg <= dout; + wait until rising_edge(clk); + re <= '0'; + end process; + +------------------------------------------------------------------------------------------ + +STIMULUS: process + + + begin + + wait for 3*CLK_PERIOD; + rst <= '0'; + din <= X"10"; + wait until rising_edge(clk) and ready = '1'; + we <= '1'; + wait until rising_edge(clk) and ready = '1'; + din <= din + 1; + wait until rising_edge(clk) and ready = '1'; + we <= '0'; + wait until rising_edge(clk) and ready = '1'; + wait until rising_edge(clk) and ready = '1'; + we <= '1'; + din <= din + 1; + wait until rising_edge(clk) and ready = '1'; + din <= din + 1; + wait until rising_edge(clk) and ready = '1'; + we <= '0'; + wait until rising_edge(clk) and ready = '1'; + wait until rising_edge(clk) and ready = '1'; + wait until rising_edge(clk) and ready = '1'; + wait until rising_edge(clk) and ready = '1'; + we <= '1'; + din <= din + 1; + wait until rising_edge(clk) and ready = '1'; + we <= '1'; + din <= din + 1; + wait until rising_edge(clk) and ready = '1'; + we <= '1'; + din <= din + 1; + wait until rising_edge(clk) and ready = '1'; + we <= '1'; + din <= din + 1; + wait until rising_edge(clk) and ready = '1'; + we <= '1'; + din <= din + 1; + wait until rising_edge(clk) and ready = '1'; + we <= '1'; + din <= din + 1; + wait until rising_edge(clk) and ready = '1'; + + + wait; + + end process; + +end architecture behave; diff --git a/lib/misc/tb_ram_wb.vhd b/lib/misc/tb_ram_wb.vhd new file mode 100644 index 0000000..b165069 --- /dev/null +++ b/lib/misc/tb_ram_wb.vhd @@ -0,0 +1,408 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: testbench for system test using Xilinx ML-402 + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +use std.textio.all; -- Imports the standard textio package. + +ENTITY tb_ram_wb IS +END tb_ram_wb; + +ARCHITECTURE behavior OF tb_ram_wb IS + + constant CLK_PERIOD : time := 10 ns; + signal CLK_O : std_logic := '1'; + signal RST_O : std_logic := '1'; + signal CYC_O : std_logic := '0'; + signal STB_O : std_logic := '0'; + signal WE_O : std_logic := '0'; + signal SEL_O : unsigned(3 downto 0) := (others => '1'); + signal ACK_I : std_logic; + signal MRDY_O : std_logic := '1'; + signal SRDY_I : std_logic; + signal ADDR_O : unsigned(31 downto 0) := (others => '-'); + signal DAT_I : unsigned(31 downto 0); + signal DAT_O : unsigned(31 downto 0) := (others => '-'); + + signal dout_rst : std_logic := '0'; + signal dout_reg : unsigned(31 downto 0); + signal dout_cnt : natural range 0 to 255; + +BEGIN + +inst_ram_wb : entity work.ram_wb + PORT MAP + ( + RST_I => RST_O, + CLK_I => CLK_O, + CYC_I => CYC_O, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I, + SRDY_O => SRDY_I, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I + ); + +read_register: + process(CLK_O) + begin + if rising_edge(CLK_O) then + if dout_rst = '1' then + dout_cnt <= 0; + elsif ACK_I = '1' and WE_O = '0' then + dout_reg <= DAT_I; + dout_cnt <= dout_cnt + 1; + end if; + end if; + end process; + +CLK_GEN: process + begin + wait for CLK_PERIOD/2; + CLK_O <= not CLK_O; + end process; + +STIMULUS: process + + begin + + wait for 3*CLK_PERIOD; + RST_O <= '0'; + + -- 8 single cycles + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '1'; + DAT_O <= X"1234_0000"; + ADDR_O <= X"0000_0000"; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + DAT_O <= DAT_O + 1; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + wait until rising_edge(CLK_O) and ACK_I = '1'; + CYC_O <= '0'; + + + -- 8-word burst cycle + wait for 3*CLK_PERIOD; + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '0'; + ADDR_O <= X"0000_0000"; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + + wait until rising_edge(CLK_O) and dout_cnt = 7; + CYC_O <= '0'; + + wait for 3*CLK_PERIOD; + wait until rising_edge(CLK_O); + -- 1-word burst cycle + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '1'; + SEL_O <= "0011"; + ADDR_O <= X"0000_0080"; + DAT_O <= X"DEADBEEF"; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + wait until rising_edge(CLK_O) and ACK_I = '1'; + CYC_O <= '0'; + + wait for 3*CLK_PERIOD; + wait until rising_edge(CLK_O); + -- 1-word burst cycle + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '0'; + ADDR_O <= X"0000_0080"; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + wait until rising_edge(CLK_O) and ACK_I = '1'; + CYC_O <= '0'; + + -- 8-word burst cycle + wait for 3*CLK_PERIOD; + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + CYC_O <= '1'; + STB_O <= '1'; + WE_O <= '0'; + ADDR_O <= X"0000_0000"; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + MRDY_O <= '0'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '1'; + MRDY_O <= '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + + wait until rising_edge(CLK_O) and dout_cnt = 54; + CYC_O <= '0'; + + wait; + + end process; + +END; diff --git a/lib/misc/tb_rom_wb.vhd b/lib/misc/tb_rom_wb.vhd new file mode 100644 index 0000000..0e414f9 --- /dev/null +++ b/lib/misc/tb_rom_wb.vhd @@ -0,0 +1,223 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: testbench for system test using Xilinx ML-402 + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +use std.textio.all; -- Imports the standard textio package. + +ENTITY tb_rom_wb IS +END tb_rom_wb; + +ARCHITECTURE behavior OF tb_rom_wb IS + + constant CLK_PERIOD : time := 10 ns; + signal CLK_O : std_logic := '1'; + signal RST_O : std_logic := '1'; + signal CYC_O : std_logic := '0'; + signal STB_O : std_logic := '0'; + signal ACK_I : std_logic; + signal MRDY_O : std_logic := '1'; + signal SRDY_I : std_logic; + signal ADDR_O : unsigned(31 downto 0) := (others => '-'); + signal DAT_I : unsigned(31 downto 0); + + signal dout_rst : std_logic := '0'; + signal dout_reg : unsigned(31 downto 0); + signal dout_cnt : natural range 0 to 255; + +BEGIN + +inst_rom_wb : entity work.rom_wb + PORT MAP + ( + RST_I => RST_O, + CLK_I => CLK_O, + CYC_I => CYC_O, + STB_I => STB_O, + ACK_O => ACK_I, + SRDY_O => SRDY_I, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_O => DAT_I + ); + +read_register: + process(CLK_O) + begin + if rising_edge(CLK_O) then + if dout_rst = '1' then + dout_cnt <= 0; + elsif ACK_I = '1' then + dout_reg <= DAT_I; + dout_cnt <= dout_cnt + 1; + end if; + end if; + end process; + +CLK_GEN: process + begin + wait for CLK_PERIOD/2; + CLK_O <= not CLK_O; + end process; + +STIMULUS: process + + begin + + wait for 3*CLK_PERIOD; + RST_O <= '0'; + + -- 8-word burst cycle + wait for 3*CLK_PERIOD; + dout_rst <= '1'; + wait until rising_edge(CLK_O); + dout_rst <= '0'; + CYC_O <= '1'; + STB_O <= '1'; + ADDR_O <= X"0000_0180"; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + MRDY_O <= '0'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '1'; + MRDY_O <= '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + ADDR_O <= ADDR_O + 4; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + + wait until rising_edge(CLK_O) and dout_cnt = 54; + CYC_O <= '0'; + + wait; + + end process; + +END;