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- cleaned up unused signals

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- fixed sensitivity list issues

git-svn-id: http://moon:8086/svn/vhdl/trunk@1084 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-15 16:36:33 +00:00
parent 182e68126e
commit 691706ef57
6 changed files with 57 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/mips_alu.vhd
+2 -4
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@@ -50,8 +50,8 @@ architecture Behavioral of alu is
signal xor_res : unsigned (data_width-1 downto 0);
signal nor_res : unsigned (data_width-1 downto 0);
signal or_res : unsigned (data_width-1 downto 0);
signal eq, sa, sb, sr, c, z : STD_LOGIC;
signal lts, ltu : STD_LOGIC;
signal eq, sa, sb, sr, c : STD_LOGIC;
signal lts, ltu : STD_LOGIC;
--------------------------------------------------------------------------
begin
@@ -60,11 +60,9 @@ begin
sa <= op1_in(op1_in'left);
sb <= op2_in(op2_in'left);
sr <= sum_res(sum_res'left);
z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0';
flags.uvf <= (not ctrl.add) and ((sa and (not sb) and (not sr)) or ((not sa) and sb and sr));
flags.ovf <= ctrl.add and ((sa and sb and (not sr)) or ((not sa) and (not sb) and sr));
-- lts <= (not eq) and (((not c) and sa and sb) or (((not sr) and sa) or (sa and (not sb)) or (sr and (not sb))));
lts <= not eq and ((not c and sa) or (not sb and sa) or (not sb and sr));
ltu <= (not eq) and (not c);
lib/CPUs/MIPS/src/core/mips_cop.vhd
-1
View File
@@ -64,7 +64,6 @@ architecture Behavioral of cop is
signal test_reg : word_t;
signal test_reg_we : STD_LOGIC;
signal stat_reg_we : STD_LOGIC;
signal eflags_reg_we : STD_LOGIC;
signal epc_reg_we : STD_LOGIC;
signal code_reg_we : STD_LOGIC;
signal ip_reg_we : STD_LOGIC;
lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+53 -47
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@@ -34,12 +34,10 @@ entity pipeline is
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
imem_err : in STD_LOGIC;
imem_rdy : in STD_LOGIC;
imem_en : out STD_LOGIC;
imem_addr : out word_t;
imem_data : in word_t;
dmem_err : in STD_LOGIC;
dmem_rdy : in STD_LOGIC;
dmem_en : out STD_LOGIC;
dmem_we : out STD_LOGIC;
@@ -309,25 +307,27 @@ proc_stage_pc_next:
proc_stage_branch:
process(clk_2)
begin
if rising_edge(clk_2) and branch_ce = '1' then
pc.branch_take <= '0';
if EX_stage.ctrl.branch = '1' then
if rising_edge(clk_2) then
if branch_ce = '1' then
pc.branch_take <= '0';
if EX_stage.ctrl.branch = '1' then
case EX_stage.ctrl.bc_src is
case EX_stage.ctrl.bc_src is
when bc_eq_ne =>
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
when bc_eq_ne =>
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
when bc_lez_gtz =>
pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
when bc_lez_gtz =>
pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
when bc_ltz_gez =>
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
when bc_ltz_gez =>
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
@@ -631,9 +631,11 @@ proc_wptr_mux:
proc_stage_bcu_op:
process(clk_1)
begin
if rising_edge(clk_1) and sdu.EX_stall = '0' then
bcu_op_a <= ID_stage.reg_a;
bcu_op_b <= ID_stage.reg_b;
if rising_edge(clk_1) then
if sdu.EX_stall = '0' then
bcu_op_a <= ID_stage.reg_a;
bcu_op_b <= ID_stage.reg_b;
end if;
end if;
end process;
@@ -644,22 +646,24 @@ alu_op2_mux:
variable data : word_t;
begin
if rising_edge(clk_1) and sdu.EX_stall = '0' then
data := ID_stage.reg_b;
case ID_stage.ctrl.alu.op2_src is
when alu_src_reg =>
if rising_edge(clk_1) then
if sdu.EX_stall = '0' then
data := ID_stage.reg_b;
when alu_src_imm =>
data := ID_stage.imm;
case ID_stage.ctrl.alu.op2_src is
when others => null;
when alu_src_reg =>
data := ID_stage.reg_b;
end case;
when alu_src_imm =>
data := ID_stage.imm;
EX_stage.alu_op2 <= data;
when others => null;
end case;
EX_stage.alu_op2 <= data;
end if;
end if;
end process;
@@ -670,28 +674,30 @@ shifter_sa_mux:
variable data_inv : shamt_t;
begin
if rising_edge(clk_1) and sdu.EX_stall = '0' then
data := ID_stage.reg_a(4 downto 0);
case ID_stage.ctrl.shamt2_srcsel is
if rising_edge(clk_1) then
if sdu.EX_stall = '0' then
data := ID_stage.reg_a(4 downto 0);
case ID_stage.ctrl.shamt2_srcsel is
when sa_src_reg =>
data := ID_stage.reg_a(4 downto 0);
when sa_src_reg =>
data := ID_stage.reg_a(4 downto 0);
when sa_src_imm =>
data := ID_stage.shamt;
when sa_src_imm =>
data := ID_stage.shamt;
when others => null;
when others => null;
end case;
data_inv := not data + 1;
if ID_stage.ctrl.alu.shift_right = '0' then
EX_stage.shift_ctrl.shamt_rnd <= data_inv;
else
EX_stage.shift_ctrl.shamt_rnd <= data;
end if;
EX_stage.shift_ctrl.shamt_nrm <= data;
EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right;
EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith;
end case;
data_inv := not data + 1;
if ID_stage.ctrl.alu.shift_right = '0' then
EX_stage.shift_ctrl.shamt_rnd <= data_inv;
else
EX_stage.shift_ctrl.shamt_rnd <= data;
end if;
EX_stage.shift_ctrl.shamt_nrm <= data;
EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right;
EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith;
end if;
end if;
end process;
lib/CPUs/MIPS/src/core/mips_top.vhd
-4
View File
@@ -70,12 +70,10 @@ architecture rtl of mips_top is
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
imem_err : in STD_LOGIC;
imem_rdy : in STD_LOGIC;
imem_en : out STD_LOGIC;
imem_addr : out word_t;
imem_data : in word_t;
dmem_err : in STD_LOGIC;
dmem_rdy : in STD_LOGIC;
dmem_en : out STD_LOGIC;
dmem_we : out STD_LOGIC;
@@ -222,12 +220,10 @@ inst_pipeline: pipeline
rst => cpu_rst,
clk => cpu_clk,
ce => cpu_run,
imem_err => imem_err,
imem_rdy => imem_rdy,
imem_en => imem_en,
imem_addr => imem_addr,
imem_data => imem_din,
dmem_err => dmem_err,
dmem_rdy => dmem_rdy,
dmem_en => dmem_en,
dmem_we => dmem_we,
lib/FIFO/src/fifo_async.vhd
+1 -2
View File
@@ -63,7 +63,6 @@ architecture Behavioral of fifo_async is
signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : std_logic;
signal empty : std_logic;
signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC;
signal rinc : std_logic;
@@ -95,7 +94,7 @@ begin
ptr_r => ptr_r,
fifo_full => full,
fifo_empty => empty,
fifo_pre_full => pre_full,
fifo_pre_full => open,
fifo_pre_empty => pre_empty,
fifo_afull => fifo_afull,
fifo_aempty => fifo_aempty
lib/FIFO/src/fifo_sync.vhd
+1 -2
View File
@@ -63,7 +63,6 @@ architecture Behavioral of fifo_sync is
signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : STD_LOGIC;
signal empty : std_logic;
signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC;
signal rinc : std_logic;
@@ -94,7 +93,7 @@ inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
ptr_r => ptr_r,
fifo_full => full,
fifo_empty => empty,
fifo_pre_full => pre_full,
fifo_pre_full => open,
fifo_pre_empty => pre_empty,
fifo_afull => fifo_afull,
fifo_aempty => fifo_aempty