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- fixed type cast in test bench

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1151 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-22 06:14:32 +00:00
parent 1d6bd6979a
commit 62499069a2
2 changed files with 10 additions and 10 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+4 -4
View File
@@ -193,8 +193,8 @@ inst_clockgen : entity work.clockgen
i_mt46v16m16_0 : entity work.mt46v16m16 i_mt46v16m16_0 : entity work.mt46v16m16
port map port map
( (
dq => std_logic_vector(part_data(15 downto 0)), unsigned(dq) => std_logic_vector(part_data(15 downto 0)),
dqs => std_logic_vector(part_dqs(1 downto 0)), unsigned(dqs) => std_logic_vector(part_dqs(1 downto 0)),
addr => std_logic_vector(part_addr), addr => std_logic_vector(part_addr),
ba => std_logic_vector(part_ba), ba => std_logic_vector(part_ba),
clk => part_clk_p, clk => part_clk_p,
@@ -211,8 +211,8 @@ i_mt46v16m16_0 : entity work.mt46v16m16
i_mt46v16m16_1 : entity work.mt46v16m16 i_mt46v16m16_1 : entity work.mt46v16m16
port map port map
( (
dq => std_logic_vector(part_data(31 downto 16)), unsigned(dq) => std_logic_vector(part_data(31 downto 16)),
dqs => std_logic_vector(part_dqs(3 downto 2)), unsigned(dqs) => std_logic_vector(part_dqs(3 downto 2)),
addr => std_logic_vector(part_addr), addr => std_logic_vector(part_addr),
ba => std_logic_vector(part_ba), ba => std_logic_vector(part_ba),
clk => part_clk_p, clk => part_clk_p,
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+4 -4
View File
@@ -189,8 +189,8 @@ inst_clockgen : entity work.clockgen
i_mt46v16m16_0 : entity work.mt46v16m16 i_mt46v16m16_0 : entity work.mt46v16m16
port map port map
( (
dq => std_logic_vector(part_data(15 downto 0)), unsigned(dq) => std_logic_vector(part_data(15 downto 0)),
dqs => std_logic_vector(part_dqs(1 downto 0)), unsigned(dqs) => std_logic_vector(part_dqs(1 downto 0)),
addr => std_logic_vector(part_addr), addr => std_logic_vector(part_addr),
ba => std_logic_vector(part_ba), ba => std_logic_vector(part_ba),
clk => part_clk_p, clk => part_clk_p,
@@ -207,8 +207,8 @@ i_mt46v16m16_0 : entity work.mt46v16m16
i_mt46v16m16_1 : entity work.mt46v16m16 i_mt46v16m16_1 : entity work.mt46v16m16
port map port map
( (
dq => std_logic_vector(part_data(31 downto 16)), unsigned(dq) => std_logic_vector(part_data(31 downto 16)),
dqs => std_logic_vector(part_dqs(3 downto 2)), unsigned(dqs) => std_logic_vector(part_dqs(3 downto 2)),
addr => std_logic_vector(part_addr), addr => std_logic_vector(part_addr),
ba => std_logic_vector(part_ba), ba => std_logic_vector(part_ba),
clk => part_clk_p, clk => part_clk_p,