diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
index fdfd07d..c938268 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
@@ -193,8 +193,8 @@ inst_clockgen : entity work.clockgen
 i_mt46v16m16_0 : entity work.mt46v16m16 
       port map
       (
-         dq    => std_logic_vector(part_data(15 downto 0)),
-         dqs   => std_logic_vector(part_dqs(1 downto 0)),
+         unsigned(dq)	=> std_logic_vector(part_data(15 downto 0)),
+         unsigned(dqs)	=> std_logic_vector(part_dqs(1 downto 0)),
          addr  => std_logic_vector(part_addr),
          ba    => std_logic_vector(part_ba),
          clk   => part_clk_p,
@@ -211,8 +211,8 @@ i_mt46v16m16_0 : entity work.mt46v16m16
 i_mt46v16m16_1 : entity work.mt46v16m16 
       port map
       (
-         dq    => std_logic_vector(part_data(31 downto 16)),
-         dqs   => std_logic_vector(part_dqs(3 downto 2)),
+         unsigned(dq)	=> std_logic_vector(part_data(31 downto 16)),
+         unsigned(dqs)	=> std_logic_vector(part_dqs(3 downto 2)),
          addr  => std_logic_vector(part_addr),
          ba    => std_logic_vector(part_ba),
          clk   => part_clk_p,
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
index 9673d37..804f761 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
@@ -189,8 +189,8 @@ inst_clockgen : entity work.clockgen
 i_mt46v16m16_0 : entity work.mt46v16m16 
       port map
       (
-         dq    => std_logic_vector(part_data(15 downto 0)),
-         dqs   => std_logic_vector(part_dqs(1 downto 0)),
+         unsigned(dq)	=> std_logic_vector(part_data(15 downto 0)),
+         unsigned(dqs)	=> std_logic_vector(part_dqs(1 downto 0)),
          addr  => std_logic_vector(part_addr),
          ba    => std_logic_vector(part_ba),
          clk   => part_clk_p,
@@ -207,10 +207,10 @@ i_mt46v16m16_0 : entity work.mt46v16m16
 i_mt46v16m16_1 : entity work.mt46v16m16 
       port map
       (
-         dq    => std_logic_vector(part_data(31 downto 16)),
-         dqs   => std_logic_vector(part_dqs(3 downto 2)),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
+         unsigned(dq)	=> std_logic_vector(part_data(31 downto 16)),
+         unsigned(dqs)	=> std_logic_vector(part_dqs(3 downto 2)),
+         addr => std_logic_vector(part_addr),
+         ba	=> std_logic_vector(part_ba),
          clk   => part_clk_p,
          clk_n => part_clk_n,
          cke   => part_cke,