jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- cleaned up

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@752 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-13 10:51:47 +00:00
parent 28056fbdff
commit 60d59f2f07
3 changed files with 19 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/FIFO/src/tb_gray_counter.vhd
+8 -6
View File
@@ -11,7 +11,7 @@
-- Description:
--
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.2 2010-02-13 10:50:47 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -65,15 +65,17 @@ inst_gray_counter : entity work.gray_counter
wait for 4*PERIOD;
rst <= '0';
wait for 1*PERIOD;
wait until rising_edge(clk);
ce <= '1';
wait for 2*PERIOD;
wait until rising_edge(clk);
ce <= '0';
wait for 3*PERIOD;
ce <= '0';
wait for 4*PERIOD;
wait until rising_edge(clk);
ce <= '1';
wait for 1*PERIOD;
wait until rising_edge(clk);
ce <= '0';
wait for 1*PERIOD;
wait until rising_edge(clk);
ce <= '1';
wait;