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- cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/trunk@719 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 13:56:25 +00:00
parent b8a69d571a
commit 5dae6793f2
2 changed files with 5 additions and 11 deletions
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lib/FIFO/src/fifo_sync.vhd
+3 -9
View File
@@ -58,9 +58,6 @@ architecture Behavioral of fifo_sync is
signal ptr_w : unsigned (addr_width-1 downto 0); signal ptr_w : unsigned (addr_width-1 downto 0);
signal ptr_r : unsigned (addr_width-1 downto 0); signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : STD_LOGIC; signal full : STD_LOGIC;
signal empty : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal pre_full : STD_LOGIC; signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC; signal pre_empty : STD_LOGIC;
@@ -69,9 +66,6 @@ begin
mem_wr_en <= not full; mem_wr_en <= not full;
mem_rd_en <= not pre_empty; mem_rd_en <= not pre_empty;
fifo_full <= full; fifo_full <= full;
fifo_empty <= empty;
fifo_afull <= almost_full;
fifo_aempty <= almost_empty;
inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
GENERIC MAP GENERIC MAP
@@ -89,11 +83,11 @@ inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
ptr_w => ptr_w, ptr_w => ptr_w,
ptr_r => ptr_r, ptr_r => ptr_r,
fifo_full => full, fifo_full => full,
fifo_empty => empty, fifo_empty => fifo_empty,
fifo_pre_full => pre_full, fifo_pre_full => pre_full,
fifo_pre_empty => pre_empty, fifo_pre_empty => pre_empty,
fifo_afull => almost_full, fifo_afull => fifo_afull,
fifo_aempty => almost_empty fifo_aempty => fifo_aempty
); );
lib/FIFO/src/sync_fifo_ctrl.vhd
+2 -2
View File
@@ -163,7 +163,7 @@ proc_flag_write:
end process; end process;
proc_ptr_w: proc_ptr_w:
process(rst, clk, pW, write, full) process(rst, clk, pW, write)
begin begin
if rst = '1' then if rst = '1' then
pW <= to_unsigned(0, addr_width); pW <= to_unsigned(0, addr_width);
@@ -181,7 +181,7 @@ proc_ptr_w:
end process; end process;
proc_ptr_r: proc_ptr_r:
process(rst, clk, pR_next, pR, read, empty) process(rst, clk, pR_next, pR, read)
begin begin
if rst = '1' then if rst = '1' then
pR <= to_unsigned(0, addr_width); pR <= to_unsigned(0, addr_width);