From 5dae6793f27865143758ee508e480eb5350b4ef9 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 7 Feb 2010 13:56:25 +0000 Subject: [PATCH] - cleaned up Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@719 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/FIFO/src/fifo_sync.vhd | 12 +++--------- lib/FIFO/src/sync_fifo_ctrl.vhd | 4 ++-- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/lib/FIFO/src/fifo_sync.vhd b/lib/FIFO/src/fifo_sync.vhd index 810ba7c..a5aa4c8 100644 --- a/lib/FIFO/src/fifo_sync.vhd +++ b/lib/FIFO/src/fifo_sync.vhd @@ -58,9 +58,6 @@ architecture Behavioral of fifo_sync is signal ptr_w : unsigned (addr_width-1 downto 0); signal ptr_r : unsigned (addr_width-1 downto 0); signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; signal pre_full : STD_LOGIC; signal pre_empty : STD_LOGIC; @@ -69,9 +66,6 @@ begin mem_wr_en <= not full; mem_rd_en <= not pre_empty; fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl GENERIC MAP @@ -89,11 +83,11 @@ inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl ptr_w => ptr_w, ptr_r => ptr_r, fifo_full => full, - fifo_empty => empty, + fifo_empty => fifo_empty, fifo_pre_full => pre_full, fifo_pre_empty => pre_empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty + fifo_afull => fifo_afull, + fifo_aempty => fifo_aempty ); diff --git a/lib/FIFO/src/sync_fifo_ctrl.vhd b/lib/FIFO/src/sync_fifo_ctrl.vhd index c0f293e..4ee024d 100644 --- a/lib/FIFO/src/sync_fifo_ctrl.vhd +++ b/lib/FIFO/src/sync_fifo_ctrl.vhd @@ -163,7 +163,7 @@ proc_flag_write: end process; proc_ptr_w: - process(rst, clk, pW, write, full) + process(rst, clk, pW, write) begin if rst = '1' then pW <= to_unsigned(0, addr_width); @@ -181,7 +181,7 @@ proc_ptr_w: end process; proc_ptr_r: - process(rst, clk, pR_next, pR, read, empty) + process(rst, clk, pR_next, pR, read) begin if rst = '1' then pR <= to_unsigned(0, addr_width);