- refactored
git-svn-id: http://moon:8086/svn/vhdl/trunk@1531 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,126 @@
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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library work;
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use work.utils_pkg.all;
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ENTITY ram_wb IS
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GENERIC
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(
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NUM_WORDS : integer := 64
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);
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Port
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0)
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);
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END ram_wb;
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ARCHITECTURE behavior OF ram_wb IS
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constant addr_width : natural := NextExpBaseTwo(NUM_WORDS);
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signal ram_en : std_logic;
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signal we : unsigned(3 downto 0);
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signal re : std_logic;
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begin
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SRDY_O <= CYC_I;
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ram_en <= CYC_I and STB_I and MRDY_I;
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we <= SEL_I and (3 downto 0 => ram_en and WE_I);
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re <= ram_en and not WE_I;
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data_valid_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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ACK_O <= '0';
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else
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ACK_O <= re;
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end if;
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end if;
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end process;
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inst_ram_0 : entity work.dpram_1w1r1c_ra
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GENERIC MAP
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(
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addr_width => addr_width,
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data_width => 8
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)
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PORT MAP
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(
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clk => CLK_I,
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we_a => we(0),
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re_b => '1',
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addr_a => ADDR_I(addr_width+1 downto 2),
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addr_b => ADDR_I(addr_width+1 downto 2),
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din_a => DAT_I(7 downto 0),
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dout_b => DAT_O(7 downto 0)
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);
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inst_ram_1 : entity work.dpram_1w1r1c_ra
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GENERIC MAP
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(
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addr_width => addr_width,
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data_width => 8
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)
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PORT MAP
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(
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clk => CLK_I,
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we_a => we(1),
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re_b => '1',
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addr_a => ADDR_I(addr_width+1 downto 2),
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addr_b => ADDR_I(addr_width+1 downto 2),
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din_a => DAT_I(15 downto 8),
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dout_b => DAT_O(15 downto 8)
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);
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inst_ram_2 : entity work.dpram_1w1r1c_ra
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GENERIC MAP
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(
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addr_width => addr_width,
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data_width => 8
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)
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PORT MAP
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(
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clk => CLK_I,
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we_a => we(2),
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re_b => '1',
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addr_a => ADDR_I(addr_width+1 downto 2),
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addr_b => ADDR_I(addr_width+1 downto 2),
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din_a => DAT_I(23 downto 16),
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dout_b => DAT_O(23 downto 16)
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);
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inst_ram_3 : entity work.dpram_1w1r1c_ra
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GENERIC MAP
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(
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addr_width => addr_width,
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data_width => 8
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)
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PORT MAP
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(
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clk => CLK_I,
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we_a => we(3),
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re_b => '1',
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addr_a => ADDR_I(addr_width+1 downto 2),
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addr_b => ADDR_I(addr_width+1 downto 2),
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din_a => DAT_I(31 downto 24),
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dout_b => DAT_O(31 downto 24)
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);
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end behavior;
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,62 @@
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY rom_wb IS
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Port
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0)
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);
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END rom_wb;
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ARCHITECTURE behavior OF rom_wb IS
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COMPONENT rom
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PORT
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(
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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addr : in unsigned(31 downto 0);
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dout : out unsigned(31 downto 0)
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);
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END COMPONENT;
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signal data_en : std_logic;
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begin
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data_en <= CYC_I and STB_I and MRDY_I;
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SRDY_O <= CYC_I;
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data_valid_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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ACK_O <= '0';
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else
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ACK_O <= data_en and not WE_I;
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end if;
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end if;
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end process;
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inst_rom : rom
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PORT MAP
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(
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clk => CLK_I,
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ce => data_en,
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addr => ADDR_I,
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dout => DAT_O
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);
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end behavior;
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@@ -0,0 +1,414 @@
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-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: testbench for system test using Xilinx ML-402
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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ENTITY tb_ram_wb IS
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END tb_ram_wb;
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ARCHITECTURE behavior OF tb_ram_wb IS
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constant CLK_PERIOD : time := 10 ns;
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constant RAM_NUM_WORDS : integer := 256;
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signal CLK_O : std_logic := '1';
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signal RST_O : std_logic := '1';
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signal CYC_O : std_logic := '0';
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signal STB_O : std_logic := '0';
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signal WE_O : std_logic := '0';
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signal SEL_O : unsigned(3 downto 0) := (others => '1');
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signal ACK_I : std_logic;
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signal MRDY_O : std_logic := '1';
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signal SRDY_I : std_logic;
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signal ADDR_O : unsigned(31 downto 0) := (others => '-');
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signal DAT_I : unsigned(31 downto 0);
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signal DAT_O : unsigned(31 downto 0) := (others => '-');
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signal dout_rst : std_logic := '0';
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signal dout_reg : unsigned(31 downto 0);
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signal dout_cnt : natural range 0 to 255;
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BEGIN
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inst_ram_wb : entity work.ram_wb
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GENERIC MAP
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(
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NUM_WORDS => RAM_NUM_WORDS
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)
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PORT MAP
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(
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RST_I => RST_O,
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CLK_I => CLK_O,
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CYC_I => CYC_O,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_I,
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SRDY_O => SRDY_I,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_I
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);
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read_register:
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process(CLK_O)
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begin
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if rising_edge(CLK_O) then
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if dout_rst = '1' then
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dout_cnt <= 0;
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elsif ACK_I = '1' and WE_O = '0' then
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dout_reg <= DAT_I;
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dout_cnt <= dout_cnt + 1;
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end if;
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end if;
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end process;
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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CLK_O <= not CLK_O;
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end process;
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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RST_O <= '0';
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-- 8 single cycles
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CYC_O <= '1';
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STB_O <= '1';
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WE_O <= '1';
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DAT_O <= X"1234_CAF0";
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ADDR_O <= X"0000_0000";
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
|
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wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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DAT_O <= DAT_O + 1;
|
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ADDR_O <= ADDR_O + 4;
|
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wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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DAT_O <= DAT_O + 1;
|
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ADDR_O <= ADDR_O + 4;
|
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wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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DAT_O <= DAT_O + 1;
|
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ADDR_O <= ADDR_O + 4;
|
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wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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DAT_O <= DAT_O + 1;
|
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ADDR_O <= ADDR_O + 4;
|
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wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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DAT_O <= DAT_O + 1;
|
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ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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DAT_O <= DAT_O + 1;
|
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ADDR_O <= ADDR_O + 4;
|
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wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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DAT_O <= DAT_O + 1;
|
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ADDR_O <= ADDR_O + 4;
|
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wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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DAT_O <= DAT_O + 1;
|
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ADDR_O <= ADDR_O + 4;
|
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wait until rising_edge(CLK_O) and SRDY_I = '1';
|
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STB_O <= '0';
|
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wait until rising_edge(CLK_O);
|
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CYC_O <= '0';
|
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|
||||
|
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-- 8-word burst cycle
|
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wait for 3*CLK_PERIOD;
|
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dout_rst <= '1';
|
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wait until rising_edge(CLK_O);
|
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dout_rst <= '0';
|
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CYC_O <= '1';
|
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STB_O <= '1';
|
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WE_O <= '0';
|
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ADDR_O <= X"0000_0000";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
|
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wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
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wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
-- 1-word burst cycle
|
||||
CYC_O <= '1';
|
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STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
SEL_O <= "0011";
|
||||
ADDR_O <= X"0000_0080";
|
||||
DAT_O <= X"DEADBEEF";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
-- 1-word burst cycle
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0080";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
-- 8-word burst cycle
|
||||
wait for 3*CLK_PERIOD;
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0000";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
MRDY_O <= '0';
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '1';
|
||||
MRDY_O <= '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 54;
|
||||
CYC_O <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,224 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
ENTITY tb_rom_wb IS
|
||||
END tb_rom_wb;
|
||||
|
||||
ARCHITECTURE behavior OF tb_rom_wb IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
signal CYC_O : std_logic := '0';
|
||||
signal STB_O : std_logic := '0';
|
||||
signal ACK_I : std_logic;
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic;
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal DAT_I : unsigned(31 downto 0);
|
||||
|
||||
signal dout_rst : std_logic := '0';
|
||||
signal dout_reg : unsigned(31 downto 0);
|
||||
signal dout_cnt : natural range 0 to 255;
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_rom_wb : entity work.rom_wb
|
||||
PORT MAP
|
||||
(
|
||||
RST_I => RST_O,
|
||||
CLK_I => CLK_O,
|
||||
CYC_I => CYC_O,
|
||||
STB_I => STB_O,
|
||||
WE_I => '0',
|
||||
ACK_O => ACK_I,
|
||||
SRDY_O => SRDY_I,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_O => DAT_I
|
||||
);
|
||||
|
||||
read_register:
|
||||
process(CLK_O)
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if dout_rst = '1' then
|
||||
dout_cnt <= 0;
|
||||
elsif ACK_I = '1' then
|
||||
dout_reg <= DAT_I;
|
||||
dout_cnt <= dout_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
|
||||
-- 8-word burst cycle
|
||||
wait for 3*CLK_PERIOD;
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
ADDR_O <= X"0000_0180";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
MRDY_O <= '0';
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '1';
|
||||
MRDY_O <= '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 54;
|
||||
CYC_O <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
Reference in New Issue
Block a user