- refactored
git-svn-id: http://moon:8086/svn/vhdl/trunk@1531 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,446 @@
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-----------------------------------------------------------------------
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-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013/07/21 09:10:13 jens Exp $
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-----------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use work.busmaster_types.all;
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ENTITY tb_busmaster_sync IS
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END tb_busmaster_sync;
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ARCHITECTURE behavior OF tb_busmaster_sync IS
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constant DATA_WIDTH : integer := 32;
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constant CLK_PERIOD : time := 10 ns;
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signal CLK_O : std_logic := '1';
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signal RST_O : std_logic := '1';
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-- Master
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signal INT_O : std_logic;
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signal CYC_O : std_logic;
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signal STB_O : std_logic;
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signal WE_O : std_logic;
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signal SEL_O : unsigned(3 downto 0) := (others => '1');
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signal ACK_I : std_logic := '0';
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signal MRDY_O : std_logic := '1';
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signal SRDY_I : std_logic := '0';
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signal ADDR_O : unsigned(31 downto 0) := (others => '-');
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signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-');
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signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-');
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signal MDAT_I : unsigned(31 downto 0) := (others => '-');
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signal MDAT_O : unsigned(31 downto 0) := (others => '-');
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signal cmd_cycle_finished : std_logic;
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signal cmd_cycle_en : std_logic := '0';
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signal cmd_rdy : std_logic;
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signal cmd_we : std_logic := '0';
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signal cmd_in : bm_cmd_t;
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signal din : unsigned(31 downto 0) := (others => '-');
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signal din_rdy : std_logic;
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signal din_we : std_logic := '0';
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signal dout : unsigned(31 downto 0);
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signal dout_vld : std_logic;
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signal dout_re : std_logic := '0';
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signal rdy : std_logic := '0';
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signal read_reg : unsigned(31 downto 0) := (others => '-');
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type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
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signal state : state_t := IDLE;
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type ram_t is array (0 to 127) of unsigned(63 downto 0);
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signal ram64 : ram_t :=
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(
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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|
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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|
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|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
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|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
|
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000",
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X"0000_0000_0000_0000"
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);
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BEGIN
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MDAT_I <= MDAT_I_64(31 downto 0);
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MDAT_O_64 <= MDAT_O & MDAT_O;
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inst_uut : entity work.busmaster_sync
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GENERIC MAP
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(
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DATA_WIDTH => 32,
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FIFO_DEPTH => 2
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)
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PORT MAP
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(
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-- System signals
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rst => RST_O,
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clk => CLK_O,
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cmd_cycle_finished => cmd_cycle_finished,
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cmd_cycle_en => cmd_cycle_en,
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cmd_rdy => cmd_rdy,
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cmd_we => cmd_we,
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cmd_in => cmd_in,
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din => din,
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din_rdy => din_rdy,
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din_we => din_we,
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dout => dout,
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dout_vld => dout_vld,
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dout_re => dout_re,
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-- JBUS Master signals
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CYC_O => CYC_O,
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STB_O => STB_O,
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WE_O => WE_O,
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SEL_O => SEL_O,
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ACK_I => ACK_I,
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SRDY_I => SRDY_I,
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MRDY_O => MRDY_O,
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ADDR_O => ADDR_O,
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MDAT_I => MDAT_I,
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MDAT_O => MDAT_O
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);
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rdy_GEN: process
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begin
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-- wait for 3*CLK_PERIOD/2;
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wait until rising_edge(CLK_O);
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rdy <= not rdy;
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end process;
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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CLK_O <= not CLK_O;
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end process;
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-- Slave
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SRDY_I <= CYC_O;
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process(CLK_O)
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variable res: unsigned(63 downto 0);
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variable ram_data : unsigned(63 downto 0);
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begin
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if rising_edge(CLK_O) then
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if RST_O = '1' then
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else
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ACK_I <= '0';
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if (CYC_O and STB_O) = '1' then
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if WE_O = '0' then
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ACK_I <= '1';
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ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
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if ADDR_O(2) = '0' then
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res := ram_data;
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else
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res := ram_data(31 downto 0) & ram_data(63 downto 32);
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end if;
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elsif MRDY_O = '1' then -- WE=1
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ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
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ram_data := (others => '-');
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if ADDR_O(2) = '0' then
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if SEL_O = "11111111" then
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ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
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elsif SEL_O = "00001111" then
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ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
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elsif SEL_O = "11110000" then
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ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
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end if;
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else
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if SEL_O = "11111111" then
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ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
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elsif SEL_O = "00001111" then
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ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
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elsif SEL_O = "11110000" then
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ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
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end if;
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end if;
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end if;
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end if;
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if (CYC_O and MRDY_O) = '1' then
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MDAT_I_64 <= res;
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end if;
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end if;
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end if;
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end process;
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process(CLK_O)
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begin
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if rising_edge(CLK_O) then
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if RST_O = '1' then
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read_reg <= X"00000000";
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elsif dout_vld = '1' then
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read_reg <= dout;
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end if;
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end if;
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end process;
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dout_re <= dout_vld;
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-- Master
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STIMULUS: process
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variable result : unsigned(31 downto 0);
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procedure cmd_write_single(addr, sel, data : unsigned) is
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begin
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din <= data;
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din_we <= '1';
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wait until rising_edge(CLK_O) and din_rdy = '1';
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din_we <= '0';
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cmd_in.rw <= '1';
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cmd_in.sel <= sel;
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cmd_in.addr <= addr;
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cmd_we <= '1';
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wait until rising_edge(CLK_O) and cmd_rdy = '1';
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cmd_we <= '0';
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|
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end procedure cmd_write_single;
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procedure cmd_read_single(addr : unsigned) is
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begin
|
||||
|
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cmd_in.rw <= '0';
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cmd_in.sel <= (others => '0');
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cmd_in.addr <= addr;
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cmd_we <= '1';
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wait until rising_edge(CLK_O) and cmd_rdy = '1';
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cmd_we <= '0';
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end procedure cmd_read_single;
|
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|
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begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
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RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
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||||
wait until rising_edge(CLK_O);
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||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
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|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
wait until rising_edge(CLK_O);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
Reference in New Issue
Block a user