git-svn-id: http://moon:8086/svn/vhdl/trunk@1421 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
2021-03-21 11:14:50 +00:00
parent e3aeadebf5
commit 55ee041c08
50 changed files with 101754 additions and 0 deletions
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work
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vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
vhdl work "../../src/filter_pkg.vhd"
vhdl work "../../src/fir_stage_pkg.vhd"
vhdl work "../../src/fir_iterative_pkg.vhd"
vhdl work "../../src/fir_stage.vhd"
vhdl work "../../src/fir_iterative.vhd"
vhdl work "../../src/syn_fir_iterative.vhd"
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set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn syn_fir_iterative.prj
-ifmt mixed
-ofn syn_fir_iterative
-ofmt NGC
-p xc4vsx35-10-ff668
-top syn_fir_iterative
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso syn_fir_iterative.lso
-keep_hierarchy YES
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing YES
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
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vhdl work "W:\vhdl\lib\fixed\fixed_pkg_c.vhd"
vhdl work "W:\vhdl\projects\radio\src\filter_pkg.vhd"
vhdl work "W:\vhdl\projects\radio\src\fir_stage_pkg.vhd"
vhdl work "W:\vhdl\projects\radio\src\fir_iterative_pkg.vhd"
vhdl work "W:\vhdl\projects\radio\src\fir_stage.vhd"
vhdl work "W:\vhdl\projects\radio\src\fir_iterative.vhd"
vhdl work "W:\vhdl\projects\radio\src\syn_fir_iterative.vhd"
@@ -0,0 +1,3 @@
vhdl work "../../../../lib/src/fixed/fixed_pkg_c.vhd"
vhdl work "../../src/mix_cpx_pkg.vhd"
vhdl work "../../src/mix_cpx.vhd"
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set -tmpdir "./xst/projnav.tmp"
elaborate
-ifn mix_cpx.prj
-ifmt mixed
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vhdl work "W:\vhdl\lib\src\fixed\fixed_pkg_c.vhd"
vhdl work "W:\vhdl\projects\radio\src\mix_cpx_pkg.vhd"
vhdl work "W:\vhdl\projects\radio\src\mix_cpx.vhd"
@@ -0,0 +1 @@
work
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vhdl work "../../../../lib/src/fixed/fixed_pkg_c.vhd"
vhdl work "../../src/mix_cpx_pkg.vhd"
vhdl work "../../src/mix_cpx.vhd"
vhdl work "../../src/syn_mix_cpx.vhd"
@@ -0,0 +1,4 @@
NET "sys_clk" TNM_NET = sys_clk;
TIMESPEC TS_sys_clk = PERIOD "sys_clk" 5 ns;
OFFSET = IN 8 ns BEFORE "sys_clk";
OFFSET = OUT 12 ns AFTER "sys_clk";
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set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn syn_mix_cpx.prj
-ifmt mixed
-ofn syn_mix_cpx
-ofmt NGC
-p xc4vsx35-10-ff668
-top syn_mix_cpx
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso syn_mix_cpx.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
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vhdl work "W:\vhdl\lib\src\fixed\fixed_pkg_c.vhd"
vhdl work "W:\vhdl\projects\radio\src\mix_cpx_pkg.vhd"
vhdl work "W:\vhdl\projects\radio\src\mix_cpx.vhd"
vhdl work "W:\vhdl\projects\radio\src\syn_mix_cpx.vhd"
@@ -0,0 +1,16 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jun 02 11:22:21 Westeuropäische Sommerzeit 2007
##
vlib work
vcom -explicit -93 "../../../../lib/src/fixed/fixed_pkg_c.vhd"
vcom -explicit -93 "../../src/mix_cpx_pkg.vhd"
vcom -explicit -93 "../../src/mix_cpx.vhd"
vcom -explicit -93 "../../src/syn_mix_cpx.vhd"
vcom -explicit -93 "../../src/tb_syn_mix_cpx.vhd"
vsim -t 1ps -lib work tb_syn_mix_cpx
view wave
add wave *
do {tb_syn_mix_cpx.udo}
view structure
view signals
run 1000ns
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## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vcom -explicit -93 "../../src/syn_mix_cpx.vhd"
vcom -explicit -93 "../../src/tb_syn_mix_cpx.vhd"
vsim -t 1ps -lib work tb_syn_mix_cpx
do {tb_syn_mix_cpx.udo}
view wave
add wave *
view structure
view signals
run 1000ns
## End
@@ -0,0 +1,15 @@
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vcom -explicit -93 "./netgen/synthesis/syn_mix_cpx_synthesis.vhd"
vcom -explicit -93 "../../src/tb_syn_mix_cpx.vhd"
vsim -t 1ps -lib work tb_syn_mix_cpx
do {tb_syn_mix_cpx.udo}
view wave
add wave *
view structure
view signals
run 1000ns
## End
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-- ProjNav VHDL simulation template: tb_syn_mix_cpx.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
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work
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vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
vhdl work "../../../../lib/radio/nco/src/nco_pkg.vhd"
vhdl work "../../../../lib/radio/nco/src/waverom_dual.vhd"
vhdl work "../../../../lib/radio/nco/src/wavelut.vhd"
vhdl work "../../../../lib/radio/nco/src/nco.vhd"
vhdl work "../../src/syn_nco.vhd"
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NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 10 ns;
OFFSET = IN 8 ns BEFORE "clk";
OFFSET = OUT 12 ns AFTER "clk";
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set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn syn_nco.prj
-ifmt mixed
-ofn syn_nco
-ofmt NGC
-p xc4vsx35-10-ff668
-top syn_nco
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso syn_nco.lso
-keep_hierarchy YES
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing YES
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
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vhdl work "W:\vhdl\lib\fixed\fixed_pkg_c.vhd"
vhdl work "W:\vhdl\lib\radio\nco\src\nco_pkg.vhd"
vhdl work "W:\vhdl\lib\radio\nco\src\waverom_dual.vhd"
vhdl work "W:\vhdl\lib\radio\nco\src\wavelut.vhd"
vhdl work "W:\vhdl\lib\radio\nco\src\nco.vhd"
vhdl work "W:\vhdl\projects\radio\src\syn_nco.vhd"