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git-svn-id: http://moon:8086/svn/vhdl/trunk@1421 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 11:14:50 +00:00
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commit 55ee041c08
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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_mix_cpx
+-- Module Name:   tb_mix_cpx.vhd
+-- Project Name:  mix_cpx
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.mix_cpx_pkg.all;
+
+ENTITY syn_mix_cpx IS
+	Generic (
+		nbits_in		: integer := 12;
+		nbits_in_frac	: integer := 12;
+		nbits_out		: integer := 12;
+		nbits_out_frac	: integer := 12;
+		has_in_reg		: boolean := true;
+		has_pipe_reg	: boolean := true;
+		has_out_reg		: boolean := true;
+		rounding		: boolean := true;
+		saturating		: boolean := false
+	        );
+Port
+(
+	sys_rst			: in std_logic;
+	sys_clk			: in std_logic;
+	sys_in_valid	: in std_logic;
+	sys_x_re_in		: in signed(nbits_in-1 downto 0);
+	sys_x_im_in		: in signed(nbits_in-1 downto 0);
+	sys_y_re_in		: in signed(nbits_in-1 downto 0);
+	sys_y_im_in		: in signed(nbits_in-1 downto 0);
+	sys_out_valid	: out std_logic;
+	sys_z_re_out	: out signed(nbits_out-1 downto 0);
+	sys_z_im_out	: out signed(nbits_out-1 downto 0)
+);
+END syn_mix_cpx;
+
+ARCHITECTURE behavior OF syn_mix_cpx IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT mix_cpx
+	GENERIC
+	(
+		nbits_in		: integer;
+		nbits_in_frac	: integer;
+		nbits_out		: integer;
+		nbits_out_frac	: integer;
+		has_in_reg		: boolean;
+		has_pipe_reg	: boolean;
+		has_out_reg		: boolean;
+		rounding		: boolean;
+		saturating		: boolean
+	);
+	PORT
+	(
+		srst		: in std_logic;
+		clk			: in std_logic;
+		in_valid	: in std_logic;
+		x_re_in		: in sfixed;
+		x_im_in		: in sfixed;
+		y_re_in		: in sfixed;
+		y_im_in		: in sfixed;
+		out_valid	: out std_logic;
+		z_re_out	: out sfixed;
+		z_im_out	: out sfixed
+	);
+	END COMPONENT;
+
+	--Inputs
+	SIGNAL x_re_in     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+	SIGNAL x_im_in     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+	SIGNAL y_re_in     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+	SIGNAL y_im_in     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+
+	--Outputs
+	SIGNAL z_re_out    : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	SIGNAL z_im_out    : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+	
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	inst_mix_cpx: mix_cpx 
+	GENERIC MAP
+	(
+		nbits_in		=> nbits_in,
+		nbits_in_frac	=> nbits_in_frac,
+		nbits_out		=> nbits_out,
+		nbits_out_frac	=> nbits_out_frac,
+		has_in_reg		=> has_in_reg,
+		has_pipe_reg	=> has_pipe_reg,
+		has_out_reg		=> has_out_reg,
+		rounding		=> rounding,
+		saturating		=> saturating
+	)
+	PORT MAP
+	(
+		srst		=> sys_rst,
+		clk			=> sys_clk,
+		in_valid	=> sys_in_valid,
+		x_re_in		=> x_re_in,
+		x_im_in		=> x_im_in,
+		y_re_in		=> y_re_in,
+		y_im_in		=> y_im_in,
+		out_valid	=> sys_out_valid,
+		z_re_out	=> z_re_out,
+		z_im_out	=> z_im_out
+	);
+
+	x_re_in <= sfixed(sys_x_re_in);
+	x_im_in <= sfixed(sys_x_im_in);
+	y_re_in <= sfixed(sys_y_re_in);
+	y_im_in <= sfixed(sys_y_im_in);
+	sys_z_re_out <= signed(z_re_out);
+	sys_z_im_out <= signed(z_im_out);
+	
+END;