- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1422 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,34 @@
|
||||
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCMShutDown:Disable
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:JtagClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1 @@
|
||||
vhdl work "debounce.vhd"
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1 @@
|
||||
vhdl work "parity_bitser.vhd"
|
||||
@@ -0,0 +1,22 @@
|
||||
Release 7.1.03i - xst H.41
|
||||
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
||||
--> Parameter TMPDIR set to .
|
||||
CPU : 0.00 / 0.48 s | Elapsed : 0.00 / 0.00 s
|
||||
|
||||
-->
|
||||
=========================================================================
|
||||
* HDL Compilation *
|
||||
=========================================================================
|
||||
Compiling vhdl file "E:/work/XilinxISE/ps2if/parity_bitser.vhd" in Library work.
|
||||
Entity <parity_bitser> compiled.
|
||||
Entity <parity_bitser> (Architecture <behavioral>) compiled.
|
||||
CPU : 0.06 / 0.55 s | Elapsed : 0.00 / 0.00 s
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 66268 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 0 ( 0 filtered)
|
||||
Number of infos : 0 ( 0 filtered)
|
||||
|
||||
@@ -0,0 +1,3 @@
|
||||
work "../Common/uart/bbfifo_16x8.vhd"
|
||||
work "../Common/uart/kcuart_rx.vhd"
|
||||
work "../Common/uart/uart_rx.vhd"
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1 @@
|
||||
vhdl work "piso.vhd"
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,6 @@
|
||||
vhdl work "timeout_counter.vhd"
|
||||
vhdl work "sipo.vhd"
|
||||
vhdl work "prescaler.vhd"
|
||||
vhdl work "piso.vhd"
|
||||
vhdl work "parity_bitser.vhd"
|
||||
vhdl work "ps2_core.vhd"
|
||||
@@ -0,0 +1,55 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn ps2_core.prj
|
||||
-ifmt mixed
|
||||
-ofn ps2_core
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top ps2_core
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso ps2_core.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob false
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,2 @@
|
||||
vhdl work "debounce.vhd"
|
||||
vhdl work "ps2_phy.vhd"
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,14 @@
|
||||
vhdl work "timeout_counter.vhd"
|
||||
vhdl work "sipo.vhd"
|
||||
vhdl work "prescaler.vhd"
|
||||
vhdl work "piso.vhd"
|
||||
vhdl work "parity_bitser.vhd"
|
||||
vhdl work "debounce.vhd"
|
||||
vhdl work "E:/work/VHDL/projects/XilinxISE/Common/uart/kcuart_tx.vhd"
|
||||
vhdl work "E:/work/VHDL/projects/XilinxISE/Common/uart/kcuart_rx.vhd"
|
||||
vhdl work "E:/work/VHDL/projects/XilinxISE/Common/uart/bbfifo_16x8.vhd"
|
||||
vhdl work "ps2_phy.vhd"
|
||||
vhdl work "ps2_core.vhd"
|
||||
vhdl work "E:/work/VHDL/projects/XilinxISE/Common/uart/uart_tx.vhd"
|
||||
vhdl work "E:/work/VHDL/projects/XilinxISE/Common/uart/uart_rx.vhd"
|
||||
vhdl work "ps2if_top.vhd"
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: ps2if_top.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1,34 @@
|
||||
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCMShutDown:Disable
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:JtagClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
@@ -0,0 +1,55 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn ps2if_top.prj
|
||||
-ifmt mixed
|
||||
-ofn ps2if_top
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top ps2if_top
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso ps2if_top.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,92 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
# Bus clock nets
|
||||
NET sys_clk_in TNM_NET = "sys_clk_in";
|
||||
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
|
||||
|
||||
NET sys_clk_in LOC = AE14;
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET sys_rst_n_in LOC = D6;
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET sys_rst_n_in TIG;
|
||||
|
||||
# GPLED 0-3
|
||||
NET led<0> LOC = G5; #GPLED0
|
||||
NET led<1> LOC = G6; #GPLED1
|
||||
NET led<2> LOC = A11; #GPLED2
|
||||
NET led<3> LOC = A12; #GPLED3
|
||||
|
||||
NET "led<*>" SLEW = SLOW;
|
||||
NET "led<*>" DRIVE = 2;
|
||||
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET sys_tx LOC = W1;
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET sys_tx TIG;
|
||||
|
||||
|
||||
# Dip Switches 1-8
|
||||
#NET sys_test_in<0> LOC = U24; # DIP SW 8
|
||||
#NET sys_test_in<1> LOC = U25; # DIP SW 7
|
||||
#NET sys_test_in<2> LOC = V23; # DIP SW 6
|
||||
#NET sys_test_in<3> LOC = U23; # DIP SW 5
|
||||
#NET sys_test_in<4> LOC = U26; # DIP SW 4
|
||||
#NET sys_test_in<5> LOC = T26; # DIP SW 3
|
||||
#NET sys_test_in<6> LOC = R19; # DIP SW 2
|
||||
#NET sys_test_in<7> LOC = R20; # DIP SW 1
|
||||
#NET sys_test_in<0> IOSTANDARD = LVCMOS33;
|
||||
#NET sys_test_in<1> IOSTANDARD = LVCMOS33;
|
||||
#NET sys_test_in<2> IOSTANDARD = LVCMOS33;
|
||||
#NET sys_test_in<3> IOSTANDARD = LVCMOS33;
|
||||
#NET sys_test_in<4> IOSTANDARD = LVCMOS33;
|
||||
#NET sys_test_in<5> IOSTANDARD = LVCMOS33;
|
||||
#NET sys_test_in<6> IOSTANDARD = LVCMOS33;
|
||||
#NET sys_test_in<7> IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sys_test_in<*>" PULLDOWN;
|
||||
#NET "sys_test_in<*>" TIG;
|
||||
#NET "sys_test_in<*>" SLEW = SLOW;
|
||||
#NET "sys_test_in<*>" DRIVE = 2;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for PS/2 Ports
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
#Keyboard
|
||||
#NET ps2_keyb_clk LOC = D2;
|
||||
#NET ps2_keyb_clk SLEW = SLOW;
|
||||
#NET ps2_keyb_clk DRIVE = 2;
|
||||
#NET ps2_keyb_clk TIG;
|
||||
#NET ps2_keyb_data LOC = G9;
|
||||
#NET ps2_keyb_data SLEW = SLOW;
|
||||
#NET ps2_keyb_data DRIVE = 2;
|
||||
#NET ps2_keyb_data TIG;
|
||||
|
||||
#Mouse
|
||||
NET ps2_mouse_clk LOC = B14;
|
||||
NET ps2_mouse_clk SLEW = SLOW;
|
||||
NET ps2_mouse_clk DRIVE = 2;
|
||||
NET ps2_mouse_clk TIG;
|
||||
NET ps2_mouse_data LOC = C14;
|
||||
NET ps2_mouse_data SLEW = SLOW;
|
||||
NET ps2_mouse_data DRIVE = 2;
|
||||
NET ps2_mouse_data TIG;
|
||||
@@ -0,0 +1,18 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Mon Oct 24 20:38:21 Westeuropäische Sommerzeit 2005
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit prescaler.vhd
|
||||
vcom -93 -explicit timeout_counter.vhd
|
||||
vcom -93 -explicit sipo.vhd
|
||||
vcom -93 -explicit piso.vhd
|
||||
vcom -93 -explicit debounce.vhd
|
||||
vcom -93 -explicit parity_bitser.vhd
|
||||
vcom -93 -explicit ps2_core.vhd
|
||||
vcom -93 -explicit tb_ps2_core.vhd
|
||||
vsim -t 1ps -lib work tb_ps2_core_vhd
|
||||
do {wave_ps2_core.do}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 5000us
|
||||
@@ -0,0 +1,18 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Mon Oct 24 20:38:21 Westeuropäische Sommerzeit 2005
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit prescaler.vhd
|
||||
vcom -93 -explicit timeout_counter.vhd
|
||||
vcom -93 -explicit sipo.vhd
|
||||
vcom -93 -explicit piso.vhd
|
||||
vcom -93 -explicit debounce.vhd
|
||||
vcom -93 -explicit parity_bitser.vhd
|
||||
vcom -93 -explicit ps2_core.vhd
|
||||
vcom -93 -explicit tb_ps2_core.vhd
|
||||
vsim -t 1ps -lib work tb_ps2_core_vhd
|
||||
do {wave_ps2_core.do}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 5000us
|
||||
@@ -0,0 +1,5 @@
|
||||
-- ProjNav VHDL simulation template: tb_ps2_core_vhd.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
do {tb_ps2_core.do}
|
||||
@@ -0,0 +1,57 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/rst
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/clk
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/ce
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/write_en
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/read_en
|
||||
add wave -noupdate -format Literal /tb_ps2_core_vhd/d_in
|
||||
add wave -noupdate -format Literal /tb_ps2_core_vhd/d_out
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/timeout_load_en
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/timeout_flag
|
||||
add wave -noupdate -format Literal /tb_ps2_core_vhd/uut/read_cs
|
||||
add wave -noupdate -format Literal /tb_ps2_core_vhd/uut/data_cnt
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/data_cnt_en
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/sipo_en
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/timeout_en
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/en_us
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/input_rdy
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/ps2_clk_in
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/ps2_data_in
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/parity
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/rx_busy
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/rx_rdy
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/ps2_clk_out
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/ps2_data_out
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/tx_en
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/tx_rdy
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/tx_req
|
||||
add wave -noupdate -format Literal /tb_ps2_core_vhd/uut/write_cs
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/tx_busy
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/timeout_tx_flag
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/timeout_tx_en
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/ps2_clk_in
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/ps2_data_in
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/data_cnt_tx_en
|
||||
add wave -noupdate -format Literal /tb_ps2_core_vhd/uut/data_cnt_tx
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/piso_en
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/piso_out
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/parity_tx_en
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/parity_tx
|
||||
add wave -noupdate -format Logic /tb_ps2_core_vhd/uut/piso_load_en
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {50602858 ps} 0} {{Cursor 2} {2366768377 ps} 0}
|
||||
configure wave -namecolwidth 140
|
||||
configure wave -valuecolwidth 110
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {7090147328 ps}
|
||||
Reference in New Issue
Block a user