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git-svn-id: http://moon:8086/svn/vhdl/trunk@1422 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 11:25:09 +00:00
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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    20:52:44 10/26/05
+-- Design Name:    
+-- Module Name:    ps2_phy - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ps2_phy is
+    Port ( rst : in std_logic;
+	        clk : in std_logic;
+           ps2_clk : inout std_logic;
+           ps2_data : inout std_logic;
+           rx_clk : out std_logic;
+           rx_data : out std_logic;
+           tx_clk : in std_logic;
+           tx_data : in std_logic);
+end ps2_phy;
+
+architecture Behavioral of ps2_phy is
+
+	COMPONENT debounce
+	GENERIC (ncyc_latency : integer);
+	PORT(
+		rst : IN std_logic;
+		clk : IN std_logic;
+		input : IN std_logic;          
+		output : OUT std_logic
+		);
+	END COMPONENT;
+
+signal clk_in               : std_logic;
+signal data_in              : std_logic;
+
+begin
+
+	Inst_debounce_clk: debounce
+	GENERIC MAP (
+		ncyc_latency => 8)		
+	PORT MAP(
+		rst => rst,
+		clk => clk,
+		input => clk_in,
+		output => rx_clk
+	);
+
+	Inst_debounce_data: debounce
+	GENERIC MAP (
+		ncyc_latency => 8)		
+	PORT MAP(
+		rst => rst,
+		clk => clk,
+		input => data_in,
+		output => rx_data
+	);
+
+   IOBUF_inst_ps2_clk : IOBUF
+   generic map (
+      DRIVE => 2,
+      IBUF_DELAY_VALUE => "0",   -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only)
+      IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
+      IOSTANDARD => "DEFAULT",
+      SLEW => "SLOW")
+   port map (
+      O  => clk_in,             -- Buffer output
+      IO => ps2_clk,            -- Buffer inout port (connect directly to top-level port)
+      I  => tx_clk,             -- Buffer input
+      T  => tx_clk              -- 3-state enable input 
+   );
+
+   IOBUF_inst_ps2_data : IOBUF
+   generic map (
+      DRIVE => 2,
+      IBUF_DELAY_VALUE => "0",   -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only)
+      IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
+      IOSTANDARD => "DEFAULT",
+      SLEW => "SLOW")
+   port map (
+      O  => data_in,            -- Buffer output
+      IO => ps2_data,           -- Buffer inout port (connect directly to top-level port)
+      I  => tx_data,            -- Buffer input
+      T  => tx_data             -- 3-state enable input 
+   );
+
+end Behavioral;