- Cleaned up
git-svn-id: http://moon:8086/svn/vhdl/trunk@145 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -22,6 +22,7 @@ use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use work.fixed_pkg.all;
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use work.cordic_pkg.all;
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use work.nco_pkg.all;
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---- Uncomment the following library declaration if instantiating
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@@ -33,13 +34,7 @@ entity nco is
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Generic
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(
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nbits_wave : integer := 18;
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nbits_phase : integer := 16;
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nbits_lut_depth : integer := 12;
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nbits_dither : integer := 4;
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nbits_lfsr : integer := 12;
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q_phase : phase_relation_t := phase_90deg;
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has_pipe_reg : boolean := false;
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has_out_reg : boolean := false
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nbits_phase : integer := 16
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);
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Port
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(
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@@ -65,6 +60,7 @@ architecture Behavioral of nco is
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(
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cordic_mode : cordic_mode_t;
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z_range : real;
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gain_corr_mode : gain_corr_mode_t;
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nstages : integer;
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nbits_x_in : integer;
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nbits_y_in : integer;
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@@ -95,78 +91,41 @@ architecture Behavioral of nco is
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END COMPONENT;
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-------------------------------------------------------------------------------
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constant nbits_wave_frac : integer := nbits_wave;
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constant nbits_wave_frac : integer := nbits_wave-1;
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constant nbits_phase_frac : integer := nbits_phase;
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-------------------------------------------------------------------------------
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constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
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signal phase : signed(nbits_phase-1 downto 0);
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signal freq_in_r : signed(nbits_phase-1 downto 0);
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signal phase_in_r : signed(nbits_phase-1 downto 0);
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signal wave_i_ud, wave_q_ud : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac));
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signal phase : unsigned(nbits_phase-1 downto 0);
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signal freq_in_r : unsigned(nbits_phase-1 downto 0);
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signal phase_in_r : unsigned(nbits_phase-1 downto 0);
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signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
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signal wave_i_d, wave_q_d : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac));
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type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
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signal lfsr : lfsr_t;
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signal lfsr_out : unsigned(nbits_dither-1 downto 0);
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signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic;
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signal zin : sfixed(shi(nbits_lut_depth, nbits_lut_depth) downto slo(nbits_lut_depth, nbits_lut_depth));
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signal xin : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(0.0, shi(nbits_x_in, nbits_frac_x_in), slo(nbits_x_in, nbits_frac_x_in));
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signal yin :sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(1.0, shi(nbits_y_in, nbits_frac_y_in), slo(nbits_y_in, nbits_frac_y_in));
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signal wave_ud_valid, phase_vld : std_logic;
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signal zin_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
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signal xin : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(0.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac));
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signal yin :sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(1.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac));
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signal zout_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
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-------------------------------------------------------------------------------
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begin
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wave_out_i <= wave_i_d;
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wave_out_q <= wave_q_d;
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out_valid <= wave_d_valid;
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z_in <= to_sfixed(signed(lut_addr_d), z_in);
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------------------------------------------------------------
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proc_lfsr: process(srst, clk, lfsr, pacc_inc)
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variable lo : unsigned(nbits_dither-1 downto 0);
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begin
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if rising_edge(clk) then
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if srst = '1' then
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lfsr_valid <= '0';
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lfsr_out <= (others => '0');
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for i in lfsr'range loop
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lfsr(i) <= to_unsigned(2**i, nbits_lfsr);
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end loop;
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else
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lfsr_valid <= '0';
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if pacc_inc ='1' then
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lfsr_valid <= '1';
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lo := (others => '0');
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for i in lfsr'range loop
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if lfsr(i)(lfsr(i)'left) = '1' then
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lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
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else
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lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
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end if;
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end loop;
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for i in lfsr'range loop
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lo := lo + lfsr(i)(nbits_dither-1 downto 0);
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end loop;
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-- lo := lfsr(0)(nbits_dither downto 0);
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lfsr_out <= lo(nbits_dither-1 downto 0);
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end if;
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end if;
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end if;
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end process;
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wave_out_i <= wave_i_ud;
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wave_out_q <= wave_q_ud;
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out_valid <= wave_ud_valid;
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------------------------------------------------------------
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proc_phase_accu: process(clk, phase)
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variable phase_accu : unsigned(nbits_phase-1 downto 0);
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proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
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variable phase_accu : signed(nbits_phase-1 downto 0);
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begin
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if rising_edge(clk) then
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phase_vld <= '0';
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if srst = '1' then
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phase_accu := (others => '0');
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else
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phase_vld <= '1';
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phase <= phase_accu + phase_in_r;
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if pacc_clr = '1' then
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phase_accu := (others => '0');
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@@ -175,7 +134,8 @@ begin
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end if;
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end if;
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end if;
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phase_out <= phase;
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phase_out <= unsigned(phase);
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zin_ud <= sfixed(phase);
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end process;
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------------------------------------------------------------
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@@ -185,7 +145,7 @@ begin
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if srst = '1' then
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freq_in_r <= (others => '0');
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elsif freq_load = '1' then
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freq_in_r <= freq_in;
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freq_in_r <= signed(freq_in);
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end if;
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end if;
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end process;
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@@ -197,59 +157,44 @@ begin
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if srst = '1' then
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phase_in_r <= (others => '0');
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elsif phase_load = '1' then
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phase_in_r <= phase_in;
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phase_in_r <= signed(phase_in);
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end if;
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end if;
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end process;
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------------------------------------------------------------
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proc_pipe_reg: process(clk)
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variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
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begin
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if rising_edge(clk) then
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lut_addr_valid <= '0';
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if srst = '1' then
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lfsr_sum := (others => '0');
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elsif lfsr_valid = '1' then
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lut_addr_valid <= '1';
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lfsr_sum := lfsr_out + phase;
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end if;
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end if;
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lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
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end process;
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------------------------------------------------------------
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inst_cordic: cordic_pipe_top
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inst_cordic_ud: cordic_pipe_top
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GENERIC MAP
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(
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cordic_mode => cordic_mode_rotate,
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z_range => 1.0,
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nstages => 18,
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gain_corr_mode => gain_mode_disabled,
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nstages => nbits_phase,
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nbits_x_in => nbits_wave,
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nbits_frac_x_in => nbits_wave_frac,
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nbits_y_in => nbits_wave,
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nbits_frac_y_in => nbits_wave_frac,
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nbits_z_in => nbits_lut_depth,
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nbits_frac_z_in => nbits_lut_depth-2,
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nbits_z_in => nbits_phase,
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nbits_frac_z_in => nbits_phase_frac,
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nbits_x_out => nbits_wave,
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nbits_frac_x_out => nbits_wave_frac,
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nbits_y_out => nbits_wave,
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nbits_frac_y_out => nbits_wave_frac,
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nbits_z_out => nbits_lut_depth,
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nbits_frac_z_out => nbits_lut_depth-2
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nbits_z_out => nbits_phase,
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nbits_frac_z_out => nbits_phase_frac
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)
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PORT MAP
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(
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rst => srst,
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clk => clk,
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vld_in => lut_addr_valid,
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vld_in => phase_vld,
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xin => xin,
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yin => yin,
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zin => zin,
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xout => wave_i_d,
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yout => wave_q_d,
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zout => open,
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vld_out => wave_d_valid
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zin => zin_ud,
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xout => wave_i_ud,
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yout => wave_q_ud,
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zout => zout_ud,
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vld_out => wave_ud_valid
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);
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------------------------------------------------------------
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