From 50af9fe70d1681f3ea82aa04843bc1e2518ae05b Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 21 Dec 2008 19:53:00 +0000 Subject: [PATCH] - Cleaned up git-svn-id: http://moon:8086/svn/vhdl/trunk@145 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/radio/nco/src/nco_cordic.vhd | 133 +++++++++---------------------- 1 file changed, 39 insertions(+), 94 deletions(-) diff --git a/lib/radio/nco/src/nco_cordic.vhd b/lib/radio/nco/src/nco_cordic.vhd index 2248812..d5fa5fc 100644 --- a/lib/radio/nco/src/nco_cordic.vhd +++ b/lib/radio/nco/src/nco_cordic.vhd @@ -22,6 +22,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.MATH_REAL.ALL; USE ieee.numeric_std.ALL; use work.fixed_pkg.all; +use work.cordic_pkg.all; use work.nco_pkg.all; ---- Uncomment the following library declaration if instantiating @@ -33,13 +34,7 @@ entity nco is Generic ( nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false + nbits_phase : integer := 16 ); Port ( @@ -65,6 +60,7 @@ architecture Behavioral of nco is ( cordic_mode : cordic_mode_t; z_range : real; + gain_corr_mode : gain_corr_mode_t; nstages : integer; nbits_x_in : integer; nbits_y_in : integer; @@ -95,78 +91,41 @@ architecture Behavioral of nco is END COMPONENT; ------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; + constant nbits_wave_frac : integer := nbits_wave-1; + constant nbits_phase_frac : integer := nbits_phase; ------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 + signal phase : signed(nbits_phase-1 downto 0); + signal freq_in_r : signed(nbits_phase-1 downto 0); + signal phase_in_r : signed(nbits_phase-1 downto 0); + signal wave_i_ud, wave_q_ud : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)); - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i_d, wave_q_d : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)); - - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic; - - signal zin : sfixed(shi(nbits_lut_depth, nbits_lut_depth) downto slo(nbits_lut_depth, nbits_lut_depth)); - signal xin : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(0.0, shi(nbits_x_in, nbits_frac_x_in), slo(nbits_x_in, nbits_frac_x_in)); - signal yin :sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(1.0, shi(nbits_y_in, nbits_frac_y_in), slo(nbits_y_in, nbits_frac_y_in)); + signal wave_ud_valid, phase_vld : std_logic; + signal zin_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); + signal xin : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(0.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac)); + signal yin :sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(1.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac)); + signal zout_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); + ------------------------------------------------------------------------------- begin - wave_out_i <= wave_i_d; - wave_out_q <= wave_q_d; - out_valid <= wave_d_valid; - - z_in <= to_sfixed(signed(lut_addr_d), z_in); - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither-1 downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - lfsr_valid <= '0'; - lfsr_out <= (others => '0'); - for i in lfsr'range loop - lfsr(i) <= to_unsigned(2**i, nbits_lfsr); - end loop; - else - lfsr_valid <= '0'; - if pacc_inc ='1' then - lfsr_valid <= '1'; - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; - -- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end if; - end process; + wave_out_i <= wave_i_ud; + wave_out_q <= wave_q_ud; + out_valid <= wave_ud_valid; ------------------------------------------------------------ - proc_phase_accu: process(clk, phase) - variable phase_accu : unsigned(nbits_phase-1 downto 0); + proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r) + variable phase_accu : signed(nbits_phase-1 downto 0); begin if rising_edge(clk) then + phase_vld <= '0'; if srst = '1' then phase_accu := (others => '0'); else + phase_vld <= '1'; phase <= phase_accu + phase_in_r; if pacc_clr = '1' then phase_accu := (others => '0'); @@ -175,7 +134,8 @@ begin end if; end if; end if; - phase_out <= phase; + phase_out <= unsigned(phase); + zin_ud <= sfixed(phase); end process; ------------------------------------------------------------ @@ -185,7 +145,7 @@ begin if srst = '1' then freq_in_r <= (others => '0'); elsif freq_load = '1' then - freq_in_r <= freq_in; + freq_in_r <= signed(freq_in); end if; end if; end process; @@ -197,59 +157,44 @@ begin if srst = '1' then phase_in_r <= (others => '0'); elsif phase_load = '1' then - phase_in_r <= phase_in; + phase_in_r <= signed(phase_in); end if; end if; end process; ------------------------------------------------------------ - proc_pipe_reg: process(clk) - variable lfsr_sum : unsigned(nbits_phase-1 downto 0); - begin - if rising_edge(clk) then - lut_addr_valid <= '0'; - if srst = '1' then - lfsr_sum := (others => '0'); - elsif lfsr_valid = '1' then - lut_addr_valid <= '1'; - lfsr_sum := lfsr_out + phase; - end if; - end if; - lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end process; - ------------------------------------------------------------- - inst_cordic: cordic_pipe_top + inst_cordic_ud: cordic_pipe_top GENERIC MAP ( cordic_mode => cordic_mode_rotate, z_range => 1.0, - nstages => 18, + gain_corr_mode => gain_mode_disabled, + nstages => nbits_phase, nbits_x_in => nbits_wave, nbits_frac_x_in => nbits_wave_frac, nbits_y_in => nbits_wave, nbits_frac_y_in => nbits_wave_frac, - nbits_z_in => nbits_lut_depth, - nbits_frac_z_in => nbits_lut_depth-2, + nbits_z_in => nbits_phase, + nbits_frac_z_in => nbits_phase_frac, nbits_x_out => nbits_wave, nbits_frac_x_out => nbits_wave_frac, nbits_y_out => nbits_wave, nbits_frac_y_out => nbits_wave_frac, - nbits_z_out => nbits_lut_depth, - nbits_frac_z_out => nbits_lut_depth-2 + nbits_z_out => nbits_phase, + nbits_frac_z_out => nbits_phase_frac ) PORT MAP ( rst => srst, clk => clk, - vld_in => lut_addr_valid, + vld_in => phase_vld, xin => xin, yin => yin, - zin => zin, - xout => wave_i_d, - yout => wave_q_d, - zout => open, - vld_out => wave_d_valid + zin => zin_ud, + xout => wave_i_ud, + yout => wave_q_ud, + zout => zout_ud, + vld_out => wave_ud_valid ); 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