- added header

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git-svn-id: http://moon:8086/svn/vhdl/trunk@290 cc03376c-175c-47c8-b038-4cd826a8556b

lib/FIFO/src/fifo_sync.vhd

@@ -1,25 +1,25 @@
 -------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
+-- Project: FIFO, generic FIFOs written in VHDL
+-- Release 1
+--
 -- Copyright (C) 2007 J. Ahrensfeld
-
+--
 -- This library is free software; you can redistribute it and/or
 -- modify it under the terms of the GNU Lesser General Public
 -- License as published by the Free Software Foundation; either
 -- version 2.1 of the License, or (at your option) any later version.
-
+--
 -- This library is distributed in the hope that it will be useful,
 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 -- Lesser General Public License for more details.
-
+--
 -- You should have received a copy of the GNU Lesser General Public
 -- License along with this library; if not, write to the Free Software
 -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
+--
 -- For questions and ideas, please contact the author at jens@jayfield.org
-
+--
 -----------------------------------------------------------------------
 
 LIBRARY IEEE;
@@ -73,7 +73,7 @@ begin
 	fifo_afull	<= almost_full;
 	fifo_aempty	<= almost_empty;
 
-inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
+inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
 	GENERIC MAP
 	(
 		addr_width			=> addr_width,