From 4d5f821e7a25f7585b99eb04df6f37706e1f7e3c Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 30 Jan 2009 21:04:42 +0000 Subject: [PATCH] - added header Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@290 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/FIFO/src/fifo_async.vhd | 51 ++++++++++++++++------------------ lib/FIFO/src/fifo_ctrl_pkg.vhd | 25 +++++++++++++++-- lib/FIFO/src/fifo_sync.vhd | 18 ++++++------ lib/FIFO/src/gray_counter.vhd | 18 ++++++------ 4 files changed, 64 insertions(+), 48 deletions(-) diff --git a/lib/FIFO/src/fifo_async.vhd b/lib/FIFO/src/fifo_async.vhd index cacf393..e892bc5 100644 --- a/lib/FIFO/src/fifo_async.vhd +++ b/lib/FIFO/src/fifo_async.vhd @@ -1,31 +1,33 @@ ------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- -- Copyright (C) 2007 J. Ahrensfeld - +-- -- This library is free software; you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public -- License as published by the Free Software Foundation; either -- version 2.1 of the License, or (at your option) any later version. - +-- -- This library is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- Lesser General Public License for more details. - +-- -- You should have received a copy of the GNU Lesser General Public -- License along with this library; if not, write to the Free Software -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - +-- -- For questions and ideas, please contact the author at jens@jayfield.org - +-- ----------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; +use work.fifo_ctrl_pkg.all; + entity fifo_async is Generic ( @@ -39,8 +41,8 @@ entity fifo_async is rst : in STD_LOGIC; clk_w : in STD_LOGIC; clk_r : in STD_LOGIC; - we_w : in STD_LOGIC; - re_r : in STD_LOGIC; + we : in STD_LOGIC; + re : in STD_LOGIC; fifo_full : out STD_LOGIC; fifo_empty : out STD_LOGIC; fifo_afull : out STD_LOGIC; @@ -52,26 +54,21 @@ end fifo_async; architecture Behavioral of fifo_async is - signal buf_we_w : STD_LOGIC; signal ptr_w : unsigned (addr_width-1 downto 0); signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; + signal full : std_logic; + signal mem_we : std_logic; begin - buf_we_w <= we_w; + mem_we <= we and not full; fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; -inst_fifo_ctrl: entity work.async_fifo_ctrl + -- Instantiate the Unit Under Test (UUT) + inst_fifo_async_ctrl: entity work.fifo_async_ctrl GENERIC MAP ( - addr_width => ADDR_WIDTH, + addr_width => addr_width, almost_full_thresh => almost_full_thresh, almost_empty_thresh => almost_empty_thresh ) @@ -80,14 +77,14 @@ inst_fifo_ctrl: entity work.async_fifo_ctrl rst => rst, clk_w => clk_w, clk_r => clk_r, - we => we_w, - re => re_r, + we => we, + re => re, ptr_w => ptr_w, ptr_r => ptr_r, fifo_full => full, - fifo_empty => empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty + fifo_empty => fifo_empty, + fifo_afull => fifo_afull, + fifo_aempty => fifo_aempty ); @@ -102,7 +99,7 @@ inst_dpram_1w1r: entity work.dpram_1w1r clkb => clk_r, en_a => '1', en_b => '1', - we_a => buf_we_w, + we_a => mem_we, addr_a => ptr_w, addr_b => ptr_r, din_a => data_w, diff --git a/lib/FIFO/src/fifo_ctrl_pkg.vhd b/lib/FIFO/src/fifo_ctrl_pkg.vhd index a8c9c61..7404fc2 100644 --- a/lib/FIFO/src/fifo_ctrl_pkg.vhd +++ b/lib/FIFO/src/fifo_ctrl_pkg.vhd @@ -1,6 +1,27 @@ +------------------------------------------------------------------------- +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- ----------------------------------------------------------------------- --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/fifo_ctrl_pkg.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ + LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; diff --git a/lib/FIFO/src/fifo_sync.vhd b/lib/FIFO/src/fifo_sync.vhd index 3820f39..810ba7c 100644 --- a/lib/FIFO/src/fifo_sync.vhd +++ b/lib/FIFO/src/fifo_sync.vhd @@ -1,25 +1,25 @@ ------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- -- Copyright (C) 2007 J. Ahrensfeld - +-- -- This library is free software; you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public -- License as published by the Free Software Foundation; either -- version 2.1 of the License, or (at your option) any later version. - +-- -- This library is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- Lesser General Public License for more details. - +-- -- You should have received a copy of the GNU Lesser General Public -- License along with this library; if not, write to the Free Software -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - +-- -- For questions and ideas, please contact the author at jens@jayfield.org - +-- ----------------------------------------------------------------------- LIBRARY IEEE; @@ -73,7 +73,7 @@ begin fifo_afull <= almost_full; fifo_aempty <= almost_empty; -inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl +inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl GENERIC MAP ( addr_width => addr_width, diff --git a/lib/FIFO/src/gray_counter.vhd b/lib/FIFO/src/gray_counter.vhd index eb17fd5..66fc155 100644 --- a/lib/FIFO/src/gray_counter.vhd +++ b/lib/FIFO/src/gray_counter.vhd @@ -1,27 +1,25 @@ ------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack - +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- -- Copyright (C) 2007 J. Ahrensfeld - +-- -- This library is free software; you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public -- License as published by the Free Software Foundation; either -- version 2.1 of the License, or (at your option) any later version. - +-- -- This library is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- Lesser General Public License for more details. - +-- -- You should have received a copy of the GNU Lesser General Public -- License along with this library; if not, write to the Free Software -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - +-- -- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ +-- ----------------------------------------------------------------------- library IEEE;