jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added global clock generator

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@608 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-05 12:02:10 +00:00
parent 85779bda74
commit 4a1eafc312
3 changed files with 41 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys_sim.vhd
+19 -39
View File
@@ -357,13 +357,11 @@ ARCHITECTURE behavior OF mips_sys IS
signal nmi : std_logic;
signal eb : std_logic;
signal sdram_clk_lock : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal vga_clk_prebuf : std_logic;
signal vga_clk_lock : std_logic;
signal dcm_lock : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart0 : std_logic;
@@ -528,8 +526,7 @@ BEGIN
SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
CLK_O <= sys_clk_in;
RST_O <= not (sdram_clk_lock and vga_clk_lock);
RST_O <= not dcm_lock;
sys_flash_ssram_out:
process(CLK_O)
@@ -959,24 +956,28 @@ inst_ssram_port_wb : entity work.ssram_port_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => 100E6,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
clk_in_freq_hz => 100E6,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
sdr_clk0_out_phaseshift => 0,
sdr_clk1_out_phaseshift => 0
)
PORT MAP
(
-- Clocks and Reset
rst => rst_in, -- external async reset, low active
clk_in => CLK_O, -- system clock (e.g. 100MHz), from board
clk_fb_in => sys_sdr_clk_fb, -- feedback clock
clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => sdram_clk_lock, -- DCM locked status
error_out => open
rst => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_clk_out => CLK_O,
vga_clk_out => vga_clk,
sdr_clk0_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr_clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr_clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr_clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr_clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => dcm_lock, -- DCM locked status
error_out => open
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
@@ -1020,27 +1021,6 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
);
inst_clkgen: entity work.clkgen
GENERIC MAP
(
clk_in_freq_hz => sys_freq,
clk_out_freq_hz => tsvga.f_pxl_clk
)
PORT MAP
(
rst => rst_in,
clk_in => CLK_O,
clk_out => vga_clk_prebuf,
locked => vga_clk_lock
);
BUFG_out_clk : BUFG
port map
(
O => vga_clk, -- Clock buffer output
I => vga_clk_prebuf -- Clock buffer input
);
inst_vga_frontend : vga_frontend64
GENERIC MAP
(
@@ -1081,7 +1061,7 @@ inst_vga_frontend : vga_frontend64
-- VGA signals
vga_clk_in => vga_clk,
vga_clk_ce => vga_clk_lock,
vga_clk_ce => dcm_lock,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,